trenz.biz user SC0720 1.0 EMIO_I2C1 EMIO I2C EMIO I2C connection to SC resources SDA_I sda_i SCL_I scl_i SDA_O sda_o SCL_O scl_o SDA_T sda_t SCL_T scl_t EXT_I2C SCL_T ext_scl_t SDA_O ext_sda_o SDA_I ext_sda_i SDA_T ext_sda_t SCL_O ext_scl_o SCL_I ext_scl_i xilinx_vhdlsynthesis VHDL Synthesis vhdlSource:vivado.xilinx.com:synthesis vhdl SC0720 xilinx_vhdlsynthesis_view_fileset viewChecksum 90b51104 xilinx_vhdlbehavioralsimulation VHDL Simulation vhdlSource:vivado.xilinx.com:simulation vhdl SC0720 xilinx_vhdlbehavioralsimulation_view_fileset viewChecksum 90b51104 xilinx_xpgui UI Layout :vivado.xilinx.com:xgui.ui xilinx_xpgui_view_fileset viewChecksum 6a504774 xilinx_productguide Product Guide :vivado.xilinx.com:docs.productguide xilinx_productguide_view_fileset ext_sda_i in std_logic xilinx_vhdlsynthesis xilinx_vhdlbehavioralsimulation 1 ext_sda_o out std_logic xilinx_vhdlsynthesis xilinx_vhdlbehavioralsimulation ext_sda_t out std_logic xilinx_vhdlsynthesis xilinx_vhdlbehavioralsimulation ext_scl_i in std_logic xilinx_vhdlsynthesis xilinx_vhdlbehavioralsimulation 1 ext_scl_o out std_logic xilinx_vhdlsynthesis xilinx_vhdlbehavioralsimulation ext_scl_t out std_logic xilinx_vhdlsynthesis xilinx_vhdlbehavioralsimulation PHY_LED0 out std_logic xilinx_vhdlsynthesis xilinx_vhdlbehavioralsimulation PHY_LED1 out std_logic xilinx_vhdlsynthesis xilinx_vhdlbehavioralsimulation PHY_LED2 out std_logic xilinx_vhdlsynthesis xilinx_vhdlbehavioralsimulation PL_pin_K16 in std_logic xilinx_vhdlsynthesis xilinx_vhdlbehavioralsimulation 0 PL_pin_K19 in std_logic xilinx_vhdlsynthesis xilinx_vhdlbehavioralsimulation 0 PL_pin_L16 out std_logic xilinx_vhdlsynthesis xilinx_vhdlbehavioralsimulation PL_pin_M15 in std_logic xilinx_vhdlsynthesis xilinx_vhdlbehavioralsimulation 0 PL_pin_N15 in std_logic xilinx_vhdlsynthesis xilinx_vhdlbehavioralsimulation 0 PL_pin_P16 in std_logic xilinx_vhdlsynthesis xilinx_vhdlbehavioralsimulation 0 PL_pin_P22 in std_logic xilinx_vhdlsynthesis xilinx_vhdlbehavioralsimulation 1 PL_pin_K20 out std_logic xilinx_vhdlsynthesis xilinx_vhdlbehavioralsimulation PL_pin_N22 out std_logic xilinx_vhdlsynthesis xilinx_vhdlbehavioralsimulation sda_i out std_logic xilinx_vhdlsynthesis xilinx_vhdlbehavioralsimulation sda_o in std_logic xilinx_vhdlsynthesis xilinx_vhdlbehavioralsimulation sda_t in std_logic xilinx_vhdlsynthesis xilinx_vhdlbehavioralsimulation scl_i out std_logic xilinx_vhdlsynthesis xilinx_vhdlbehavioralsimulation scl_o in std_logic xilinx_vhdlsynthesis xilinx_vhdlbehavioralsimulation scl_t in std_logic xilinx_vhdlsynthesis xilinx_vhdlbehavioralsimulation xilinx_vhdlsynthesis_view_fileset SC0720.vhd vhdlSource CHECKSUM_90b51104 xilinx_vhdlbehavioralsimulation_view_fileset SC0720.vhd vhdlSource xilinx_xpgui_view_fileset xgui/SC0720_v1_0.tcl tclSource XGUI_VERSION_2 CHECKSUM_1820a6eb xilinx_productguide_view_fileset http://wiki.trenz-electronic.de/display/IP/SC0720 unknown TE0720 System Controller support logic 1.0 Component_Name SC0720_v1_0 zynq{xc7z014sclg484-1} zynq{xc7z020clg484-3} zynq{xc7z020clg484-2} qzynq{xq7z020cl484-2I} qzynq{xq7z020cl484-1Q} zynq{xc7z020clg484-1} qzynq{xq7z020cl484-1I} azynq{xa7z020clg484-1I} azynq{xa7z020clg484-1Q} zynq{xc7z020iclg484-1L} /BaseIP TE0720 System Controller 1.0 Trenz Electronic GmbH http://www.trenz-electronic.de 9 2015-06-20T07:51:38Z B:/cores/2014.4/zips 2014.4