trenz.biz user labtools_fmeter 1.0 refclk CLK refclk xilinx_vhdlsynthesis VHDL Synthesis vhdlSource:vivado.xilinx.com:synthesis vhdl labtools_fmeter xilinx_vhdlsynthesis_view_fileset viewChecksum b084a457 xilinx_vhdlbehavioralsimulation VHDL Simulation vhdlSource:vivado.xilinx.com:simulation vhdl labtools_fmeter xilinx_vhdlbehavioralsimulation_view_fileset viewChecksum b084a457 xilinx_xpgui UI Layout :vivado.xilinx.com:xgui.ui xilinx_xpgui_view_fileset viewChecksum 915e16d4 refclk in STD_LOGIC xilinx_vhdlsynthesis xilinx_vhdlbehavioralsimulation fin in 3 0 STD_LOGIC_VECTOR xilinx_vhdlsynthesis xilinx_vhdlbehavioralsimulation F0 out 31 0 STD_LOGIC_VECTOR xilinx_vhdlsynthesis xilinx_vhdlbehavioralsimulation F1 out 31 0 STD_LOGIC_VECTOR xilinx_vhdlsynthesis xilinx_vhdlbehavioralsimulation true F2 out 31 0 STD_LOGIC_VECTOR xilinx_vhdlsynthesis xilinx_vhdlbehavioralsimulation true F3 out 31 0 STD_LOGIC_VECTOR xilinx_vhdlsynthesis xilinx_vhdlbehavioralsimulation true F4 out 31 0 STD_LOGIC_VECTOR xilinx_vhdlsynthesis xilinx_vhdlbehavioralsimulation false F5 out 31 0 STD_LOGIC_VECTOR xilinx_vhdlsynthesis xilinx_vhdlbehavioralsimulation false F6 out 31 0 STD_LOGIC_VECTOR xilinx_vhdlsynthesis xilinx_vhdlbehavioralsimulation false F7 out 31 0 STD_LOGIC_VECTOR xilinx_vhdlsynthesis xilinx_vhdlbehavioralsimulation false F8 out 31 0 STD_LOGIC_VECTOR xilinx_vhdlsynthesis xilinx_vhdlbehavioralsimulation false F9 out 31 0 STD_LOGIC_VECTOR xilinx_vhdlsynthesis xilinx_vhdlbehavioralsimulation false F10 out 31 0 STD_LOGIC_VECTOR xilinx_vhdlsynthesis xilinx_vhdlbehavioralsimulation false F11 out 31 0 STD_LOGIC_VECTOR xilinx_vhdlsynthesis xilinx_vhdlbehavioralsimulation false F12 out 31 0 STD_LOGIC_VECTOR xilinx_vhdlsynthesis xilinx_vhdlbehavioralsimulation false F13 out 31 0 STD_LOGIC_VECTOR xilinx_vhdlsynthesis xilinx_vhdlbehavioralsimulation false F14 out 31 0 STD_LOGIC_VECTOR xilinx_vhdlsynthesis xilinx_vhdlbehavioralsimulation false F15 out 31 0 STD_LOGIC_VECTOR xilinx_vhdlsynthesis xilinx_vhdlbehavioralsimulation false F16 out 31 0 STD_LOGIC_VECTOR xilinx_vhdlsynthesis xilinx_vhdlbehavioralsimulation false F17 out 31 0 STD_LOGIC_VECTOR xilinx_vhdlsynthesis xilinx_vhdlbehavioralsimulation false F18 out 31 0 STD_LOGIC_VECTOR xilinx_vhdlsynthesis xilinx_vhdlbehavioralsimulation false F19 out 31 0 STD_LOGIC_VECTOR xilinx_vhdlsynthesis xilinx_vhdlbehavioralsimulation false F20 out 31 0 STD_LOGIC_VECTOR xilinx_vhdlsynthesis xilinx_vhdlbehavioralsimulation false F21 out 31 0 STD_LOGIC_VECTOR xilinx_vhdlsynthesis xilinx_vhdlbehavioralsimulation false F22 out 31 0 STD_LOGIC_VECTOR xilinx_vhdlsynthesis xilinx_vhdlbehavioralsimulation false F23 out 31 0 STD_LOGIC_VECTOR xilinx_vhdlsynthesis xilinx_vhdlbehavioralsimulation false F24 out 31 0 STD_LOGIC_VECTOR xilinx_vhdlsynthesis xilinx_vhdlbehavioralsimulation false F25 out 31 0 STD_LOGIC_VECTOR xilinx_vhdlsynthesis xilinx_vhdlbehavioralsimulation false F26 out 31 0 STD_LOGIC_VECTOR xilinx_vhdlsynthesis xilinx_vhdlbehavioralsimulation false F27 out 31 0 STD_LOGIC_VECTOR xilinx_vhdlsynthesis xilinx_vhdlbehavioralsimulation false F28 out 31 0 STD_LOGIC_VECTOR xilinx_vhdlsynthesis xilinx_vhdlbehavioralsimulation false F29 out 31 0 STD_LOGIC_VECTOR xilinx_vhdlsynthesis xilinx_vhdlbehavioralsimulation false F30 out 31 0 STD_LOGIC_VECTOR xilinx_vhdlsynthesis xilinx_vhdlbehavioralsimulation false F31 out 31 0 STD_LOGIC_VECTOR xilinx_vhdlsynthesis xilinx_vhdlbehavioralsimulation false update out STD_LOGIC xilinx_vhdlsynthesis xilinx_vhdlbehavioralsimulation C_CHANNELS C Channels 4 C_NUM_BITS C Num Bits 32 C_MODE C Mode 0 C_REFCLK_HZ C Refclk Hz 100000000 choice_list_07c83d4f 16 32 choice_pairs_c9e64686 0 1 xilinx_vhdlsynthesis_view_fileset labtools_fmeter.vhd vhdlSource CHECKSUM_b084a457 xilinx_vhdlbehavioralsimulation_view_fileset labtools_fmeter.vhd vhdlSource USED_IN_ipstatic xilinx_xpgui_view_fileset xgui/labtools_fmeter_v1_0.tcl tclSource CHECKSUM_ea658a1a XGUI_VERSION_2 Labtools Frequency counter v1.0 Component_Name labtools_fmeter_v1_0 C_CHANNELS Number of channels 4 C_NUM_BITS Number of bits 32 C_MODE Mode 0 C_REFCLK_HZ REF Clock in Hz 100000000 virtex7 qvirtex7 kintex7 kintex7l qkintex7 qkintex7l artix7 artix7l aartix7 qartix7 zynq qzynq azynq virtexu kintexu zynquplus kintexuplus /BaseIP Labtools Frequency Counter v1.0 19 te.lan:user:labtools_fmeter:1.0 2017-06-30T06:28:29Z b:/cores/ip/te/labtools_fmeter b:/cores/customers/hella/2017.1/design/TEC0049/test_board/ip_lib/labtools_fmeter 2017.1