BUILDDIR := ${CURDIR}/build
# TOP := top
# SOURCES := $(wildcard *.v)
# XDC := $(wildcard  $(wildcard *.xdc)  $(wildcard *.pcf)  $(wildcard *.lpf)  $(wildcard *.cst) )

# PART := xc7z020clg400-1

LOGFILE := ${BUILDDIR}/top.log

# Build design
all: ${BUILDDIR}/top.bit

${BUILDDIR}:
	mkdir -m 777 -p ${BUILDDIR} && chown -R nobody ${BUILDDIR} | true

.ONESHELL: 
${BUILDDIR}/vivado.tcl: ${BUILDDIR}
	cat << EOF > $@
	# vivado.tcl generated for caas
	# can be launched from any directory
	cd ${BUILDDIR}
	create_project -part xc7z020clg400-1 -force v_proj
	set_property target_language Verilog [current_project]
	cd ..
	read_verilog [glob *.v]
	read_xdc [glob  $(wildcard *.xdc)  $(wildcard *.pcf)  $(wildcard *.lpf)  $(wildcard *.cst) ]
	cd build
	synth_design -top top
	opt_design
	place_design
	phys_opt_design
	route_design
	write_bitstream -verbose -force top.bit
	# report_utilization -file util.rpt
	# report_timing_summary -file timing.rpt
	EOF

${BUILDDIR}/top.bit: ${BUILDDIR}/vivado.tcl
	cd ${BUILDDIR} && vivado -mode batch -source $< > ${LOGFILE} 2>&1

.PHONY: clean
clean:
	rm -rf ${BUILDDIR}