/****************************************************************************** * (c) Copyright 2010-2018 Xilinx, Inc. All rights reserved. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation; either version 2 of the License, or * (at your option) any later version. * * This program is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. * * You should have received a copy of the GNU General Public License along * with this program; if not, see * * ******************************************************************************/ /****************************************************************************/ /** * * @file ps7_init_gpl.c * * This file is automatically generated * *****************************************************************************/ #include "ps7_init_gpl.h" unsigned long ps7_pll_init_data_3_0[] = { // START: top // .. START: SLCR SETTINGS // .. UNLOCK_KEY = 0XDF0D // .. ==> 0XF8000008[15:0] = 0x0000DF0DU // .. ==> MASK : 0x0000FFFFU VAL : 0x0000DF0DU // .. EMIT_WRITE(0XF8000008, 0x0000DF0DU), // .. FINISH: SLCR SETTINGS // .. START: PLL SLCR REGISTERS // .. .. START: ARM PLL INIT // .. .. PLL_RES = 0x2 // .. .. ==> 0XF8000110[7:4] = 0x00000002U // .. .. ==> MASK : 0x000000F0U VAL : 0x00000020U // .. .. PLL_CP = 0x2 // .. .. ==> 0XF8000110[11:8] = 0x00000002U // .. .. ==> MASK : 0x00000F00U VAL : 0x00000200U // .. .. LOCK_CNT = 0xfa // .. .. ==> 0XF8000110[21:12] = 0x000000FAU // .. .. ==> MASK : 0x003FF000U VAL : 0x000FA000U // .. .. EMIT_MASKWRITE(0XF8000110, 0x003FFFF0U ,0x000FA220U), // .. .. .. START: UPDATE FB_DIV // .. .. .. PLL_FDIV = 0x28 // .. .. .. ==> 0XF8000100[18:12] = 0x00000028U // .. .. .. ==> MASK : 0x0007F000U VAL : 0x00028000U // .. .. .. EMIT_MASKWRITE(0XF8000100, 0x0007F000U ,0x00028000U), // .. .. .. FINISH: UPDATE FB_DIV // .. .. .. START: BY PASS PLL // .. .. .. PLL_BYPASS_FORCE = 1 // .. .. .. ==> 0XF8000100[4:4] = 0x00000001U // .. .. .. ==> MASK : 0x00000010U VAL : 0x00000010U // .. .. .. EMIT_MASKWRITE(0XF8000100, 0x00000010U ,0x00000010U), // .. .. .. FINISH: BY PASS PLL // .. .. .. START: ASSERT RESET // .. .. .. PLL_RESET = 1 // .. .. .. ==> 0XF8000100[0:0] = 0x00000001U // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000001U // .. .. .. EMIT_MASKWRITE(0XF8000100, 0x00000001U ,0x00000001U), // .. .. .. FINISH: ASSERT RESET // .. .. .. START: DEASSERT RESET // .. .. .. PLL_RESET = 0 // .. .. .. ==> 0XF8000100[0:0] = 0x00000000U // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000000U // .. .. .. EMIT_MASKWRITE(0XF8000100, 0x00000001U ,0x00000000U), // .. .. .. FINISH: DEASSERT RESET // .. .. .. START: CHECK PLL STATUS // .. .. .. ARM_PLL_LOCK = 1 // .. .. .. ==> 0XF800010C[0:0] = 0x00000001U // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000001U // .. .. .. EMIT_MASKPOLL(0XF800010C, 0x00000001U), // .. .. .. FINISH: CHECK PLL STATUS // .. .. .. START: REMOVE PLL BY PASS // .. .. .. PLL_BYPASS_FORCE = 0 // .. .. .. ==> 0XF8000100[4:4] = 0x00000000U // .. .. .. ==> MASK : 0x00000010U VAL : 0x00000000U // .. .. .. EMIT_MASKWRITE(0XF8000100, 0x00000010U ,0x00000000U), // .. .. .. FINISH: REMOVE PLL BY PASS // .. .. .. SRCSEL = 0x0 // .. .. .. ==> 0XF8000120[5:4] = 0x00000000U // .. .. .. ==> MASK : 0x00000030U VAL : 0x00000000U // .. .. .. DIVISOR = 0x2 // .. .. .. ==> 0XF8000120[13:8] = 0x00000002U // .. .. .. ==> MASK : 0x00003F00U VAL : 0x00000200U // .. .. .. CPU_6OR4XCLKACT = 0x1 // .. .. .. ==> 0XF8000120[24:24] = 0x00000001U // .. .. .. ==> MASK : 0x01000000U VAL : 0x01000000U // .. .. .. CPU_3OR2XCLKACT = 0x1 // .. .. .. ==> 0XF8000120[25:25] = 0x00000001U // .. .. .. ==> MASK : 0x02000000U VAL : 0x02000000U // .. .. .. CPU_2XCLKACT = 0x1 // .. .. .. ==> 0XF8000120[26:26] = 0x00000001U // .. .. .. ==> MASK : 0x04000000U VAL : 0x04000000U // .. .. .. CPU_1XCLKACT = 0x1 // .. .. .. ==> 0XF8000120[27:27] = 0x00000001U // .. .. .. ==> MASK : 0x08000000U VAL : 0x08000000U // .. .. .. CPU_PERI_CLKACT = 0x1 // .. .. .. ==> 0XF8000120[28:28] = 0x00000001U // .. .. .. ==> MASK : 0x10000000U VAL : 0x10000000U // .. .. .. EMIT_MASKWRITE(0XF8000120, 0x1F003F30U ,0x1F000200U), // .. .. FINISH: ARM PLL INIT // .. .. START: DDR PLL INIT // .. .. PLL_RES = 0x2 // .. .. ==> 0XF8000114[7:4] = 0x00000002U // .. .. ==> MASK : 0x000000F0U VAL : 0x00000020U // .. .. PLL_CP = 0x2 // .. .. ==> 0XF8000114[11:8] = 0x00000002U // .. .. ==> MASK : 0x00000F00U VAL : 0x00000200U // .. .. LOCK_CNT = 0x12c // .. .. ==> 0XF8000114[21:12] = 0x0000012CU // .. .. ==> MASK : 0x003FF000U VAL : 0x0012C000U // .. .. EMIT_MASKWRITE(0XF8000114, 0x003FFFF0U ,0x0012C220U), // .. .. .. START: UPDATE FB_DIV // .. .. .. PLL_FDIV = 0x20 // .. .. .. ==> 0XF8000104[18:12] = 0x00000020U // .. .. .. ==> MASK : 0x0007F000U VAL : 0x00020000U // .. .. .. EMIT_MASKWRITE(0XF8000104, 0x0007F000U ,0x00020000U), // .. .. .. FINISH: UPDATE FB_DIV // .. .. .. START: BY PASS PLL // .. .. .. PLL_BYPASS_FORCE = 1 // .. .. .. ==> 0XF8000104[4:4] = 0x00000001U // .. .. .. ==> MASK : 0x00000010U VAL : 0x00000010U // .. .. .. EMIT_MASKWRITE(0XF8000104, 0x00000010U ,0x00000010U), // .. .. .. FINISH: BY PASS PLL // .. .. .. START: ASSERT RESET // .. .. .. PLL_RESET = 1 // .. .. .. ==> 0XF8000104[0:0] = 0x00000001U // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000001U // .. .. .. EMIT_MASKWRITE(0XF8000104, 0x00000001U ,0x00000001U), // .. .. .. FINISH: ASSERT RESET // .. .. .. START: DEASSERT RESET // .. .. .. PLL_RESET = 0 // .. .. .. ==> 0XF8000104[0:0] = 0x00000000U // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000000U // .. .. .. EMIT_MASKWRITE(0XF8000104, 0x00000001U ,0x00000000U), // .. .. .. FINISH: DEASSERT RESET // .. .. .. START: CHECK PLL STATUS // .. .. .. DDR_PLL_LOCK = 1 // .. .. .. ==> 0XF800010C[1:1] = 0x00000001U // .. .. .. ==> MASK : 0x00000002U VAL : 0x00000002U // .. .. .. EMIT_MASKPOLL(0XF800010C, 0x00000002U), // .. .. .. FINISH: CHECK PLL STATUS // .. .. .. START: REMOVE PLL BY PASS // .. .. .. PLL_BYPASS_FORCE = 0 // .. .. .. ==> 0XF8000104[4:4] = 0x00000000U // .. .. .. ==> MASK : 0x00000010U VAL : 0x00000000U // .. .. .. EMIT_MASKWRITE(0XF8000104, 0x00000010U ,0x00000000U), // .. .. .. FINISH: REMOVE PLL BY PASS // .. .. .. DDR_3XCLKACT = 0x1 // .. .. .. ==> 0XF8000124[0:0] = 0x00000001U // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000001U // .. .. .. DDR_2XCLKACT = 0x1 // .. .. .. ==> 0XF8000124[1:1] = 0x00000001U // .. .. .. ==> MASK : 0x00000002U VAL : 0x00000002U // .. .. .. DDR_3XCLK_DIVISOR = 0x2 // .. .. .. ==> 0XF8000124[25:20] = 0x00000002U // .. .. .. ==> MASK : 0x03F00000U VAL : 0x00200000U // .. .. .. DDR_2XCLK_DIVISOR = 0x3 // .. .. .. ==> 0XF8000124[31:26] = 0x00000003U // .. .. .. ==> MASK : 0xFC000000U VAL : 0x0C000000U // .. .. .. EMIT_MASKWRITE(0XF8000124, 0xFFF00003U ,0x0C200003U), // .. .. FINISH: DDR PLL INIT // .. .. START: IO PLL INIT // .. .. PLL_RES = 0x4 // .. .. ==> 0XF8000118[7:4] = 0x00000004U // .. .. ==> MASK : 0x000000F0U VAL : 0x00000040U // .. .. PLL_CP = 0x2 // .. .. ==> 0XF8000118[11:8] = 0x00000002U // .. .. ==> MASK : 0x00000F00U VAL : 0x00000200U // .. .. LOCK_CNT = 0xfa // .. .. ==> 0XF8000118[21:12] = 0x000000FAU // .. .. ==> MASK : 0x003FF000U VAL : 0x000FA000U // .. .. EMIT_MASKWRITE(0XF8000118, 0x003FFFF0U ,0x000FA240U), // .. .. .. START: UPDATE FB_DIV // .. .. .. PLL_FDIV = 0x30 // .. .. .. ==> 0XF8000108[18:12] = 0x00000030U // .. .. .. ==> MASK : 0x0007F000U VAL : 0x00030000U // .. .. .. EMIT_MASKWRITE(0XF8000108, 0x0007F000U ,0x00030000U), // .. .. .. FINISH: UPDATE FB_DIV // .. .. .. START: BY PASS PLL // .. .. .. PLL_BYPASS_FORCE = 1 // .. .. .. ==> 0XF8000108[4:4] = 0x00000001U // .. .. .. ==> MASK : 0x00000010U VAL : 0x00000010U // .. .. .. EMIT_MASKWRITE(0XF8000108, 0x00000010U ,0x00000010U), // .. .. .. FINISH: BY PASS PLL // .. .. .. START: ASSERT RESET // .. .. .. PLL_RESET = 1 // .. .. .. ==> 0XF8000108[0:0] = 0x00000001U // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000001U // .. .. .. EMIT_MASKWRITE(0XF8000108, 0x00000001U ,0x00000001U), // .. .. .. FINISH: ASSERT RESET // .. .. .. START: DEASSERT RESET // .. .. .. PLL_RESET = 0 // .. .. .. ==> 0XF8000108[0:0] = 0x00000000U // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000000U // .. .. .. EMIT_MASKWRITE(0XF8000108, 0x00000001U ,0x00000000U), // .. .. .. FINISH: DEASSERT RESET // .. .. .. START: CHECK PLL STATUS // .. .. .. IO_PLL_LOCK = 1 // .. .. .. ==> 0XF800010C[2:2] = 0x00000001U // .. .. .. ==> MASK : 0x00000004U VAL : 0x00000004U // .. .. .. EMIT_MASKPOLL(0XF800010C, 0x00000004U), // .. .. .. FINISH: CHECK PLL STATUS // .. .. .. START: REMOVE PLL BY PASS // .. .. .. PLL_BYPASS_FORCE = 0 // .. .. .. ==> 0XF8000108[4:4] = 0x00000000U // .. .. .. ==> MASK : 0x00000010U VAL : 0x00000000U // .. .. .. EMIT_MASKWRITE(0XF8000108, 0x00000010U ,0x00000000U), // .. .. .. FINISH: REMOVE PLL BY PASS // .. .. FINISH: IO PLL INIT // .. FINISH: PLL SLCR REGISTERS // .. START: LOCK IT BACK // .. LOCK_KEY = 0X767B // .. ==> 0XF8000004[15:0] = 0x0000767BU // .. ==> MASK : 0x0000FFFFU VAL : 0x0000767BU // .. EMIT_WRITE(0XF8000004, 0x0000767BU), // .. FINISH: LOCK IT BACK // FINISH: top // EMIT_EXIT(), // }; unsigned long ps7_clock_init_data_3_0[] = { // START: top // .. START: SLCR SETTINGS // .. UNLOCK_KEY = 0XDF0D // .. ==> 0XF8000008[15:0] = 0x0000DF0DU // .. ==> MASK : 0x0000FFFFU VAL : 0x0000DF0DU // .. EMIT_WRITE(0XF8000008, 0x0000DF0DU), // .. FINISH: SLCR SETTINGS // .. START: CLOCK CONTROL SLCR REGISTERS // .. CLKACT = 0x1 // .. ==> 0XF8000128[0:0] = 0x00000001U // .. ==> MASK : 0x00000001U VAL : 0x00000001U // .. DIVISOR0 = 0xf // .. ==> 0XF8000128[13:8] = 0x0000000FU // .. ==> MASK : 0x00003F00U VAL : 0x00000F00U // .. DIVISOR1 = 0x7 // .. ==> 0XF8000128[25:20] = 0x00000007U // .. ==> MASK : 0x03F00000U VAL : 0x00700000U // .. EMIT_MASKWRITE(0XF8000128, 0x03F03F01U ,0x00700F01U), // .. CLKACT0 = 0x1 // .. ==> 0XF8000150[0:0] = 0x00000001U // .. ==> MASK : 0x00000001U VAL : 0x00000001U // .. CLKACT1 = 0x0 // .. ==> 0XF8000150[1:1] = 0x00000000U // .. ==> MASK : 0x00000002U VAL : 0x00000000U // .. SRCSEL = 0x0 // .. ==> 0XF8000150[5:4] = 0x00000000U // .. ==> MASK : 0x00000030U VAL : 0x00000000U // .. DIVISOR = 0x10 // .. ==> 0XF8000150[13:8] = 0x00000010U // .. ==> MASK : 0x00003F00U VAL : 0x00001000U // .. EMIT_MASKWRITE(0XF8000150, 0x00003F33U ,0x00001001U), // .. .. START: TRACE CLOCK // .. .. FINISH: TRACE CLOCK // .. .. CLKACT = 0x1 // .. .. ==> 0XF8000168[0:0] = 0x00000001U // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U // .. .. SRCSEL = 0x0 // .. .. ==> 0XF8000168[5:4] = 0x00000000U // .. .. ==> MASK : 0x00000030U VAL : 0x00000000U // .. .. DIVISOR = 0x8 // .. .. ==> 0XF8000168[13:8] = 0x00000008U // .. .. ==> MASK : 0x00003F00U VAL : 0x00000800U // .. .. EMIT_MASKWRITE(0XF8000168, 0x00003F31U ,0x00000801U), // .. .. SRCSEL = 0x0 // .. .. ==> 0XF8000170[5:4] = 0x00000000U // .. .. ==> MASK : 0x00000030U VAL : 0x00000000U // .. .. DIVISOR0 = 0x8 // .. .. ==> 0XF8000170[13:8] = 0x00000008U // .. .. ==> MASK : 0x00003F00U VAL : 0x00000800U // .. .. DIVISOR1 = 0x4 // .. .. ==> 0XF8000170[25:20] = 0x00000004U // .. .. ==> MASK : 0x03F00000U VAL : 0x00400000U // .. .. EMIT_MASKWRITE(0XF8000170, 0x03F03F30U ,0x00400800U), // .. .. SRCSEL = 0x0 // .. .. ==> 0XF8000180[5:4] = 0x00000000U // .. .. ==> MASK : 0x00000030U VAL : 0x00000000U // .. .. DIVISOR0 = 0x8 // .. .. ==> 0XF8000180[13:8] = 0x00000008U // .. .. ==> MASK : 0x00003F00U VAL : 0x00000800U // .. .. DIVISOR1 = 0x4 // .. .. ==> 0XF8000180[25:20] = 0x00000004U // .. .. ==> MASK : 0x03F00000U VAL : 0x00400000U // .. .. EMIT_MASKWRITE(0XF8000180, 0x03F03F30U ,0x00400800U), // .. .. SRCSEL = 0x0 // .. .. ==> 0XF8000190[5:4] = 0x00000000U // .. .. ==> MASK : 0x00000030U VAL : 0x00000000U // .. .. DIVISOR0 = 0x8 // .. .. ==> 0XF8000190[13:8] = 0x00000008U // .. .. ==> MASK : 0x00003F00U VAL : 0x00000800U // .. .. DIVISOR1 = 0x4 // .. .. ==> 0XF8000190[25:20] = 0x00000004U // .. .. ==> MASK : 0x03F00000U VAL : 0x00400000U // .. .. EMIT_MASKWRITE(0XF8000190, 0x03F03F30U ,0x00400800U), // .. .. SRCSEL = 0x0 // .. .. ==> 0XF80001A0[5:4] = 0x00000000U // .. .. ==> MASK : 0x00000030U VAL : 0x00000000U // .. .. DIVISOR0 = 0x8 // .. .. ==> 0XF80001A0[13:8] = 0x00000008U // .. .. ==> MASK : 0x00003F00U VAL : 0x00000800U // .. .. DIVISOR1 = 0x4 // .. .. ==> 0XF80001A0[25:20] = 0x00000004U // .. .. ==> MASK : 0x03F00000U VAL : 0x00400000U // .. .. EMIT_MASKWRITE(0XF80001A0, 0x03F03F30U ,0x00400800U), // .. .. CLK_621_TRUE = 0x1 // .. .. ==> 0XF80001C4[0:0] = 0x00000001U // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U // .. .. EMIT_MASKWRITE(0XF80001C4, 0x00000001U ,0x00000001U), // .. .. DMA_CPU_2XCLKACT = 0x1 // .. .. ==> 0XF800012C[0:0] = 0x00000001U // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U // .. .. USB0_CPU_1XCLKACT = 0x1 // .. .. ==> 0XF800012C[2:2] = 0x00000001U // .. .. ==> MASK : 0x00000004U VAL : 0x00000004U // .. .. USB1_CPU_1XCLKACT = 0x1 // .. .. ==> 0XF800012C[3:3] = 0x00000001U // .. .. ==> MASK : 0x00000008U VAL : 0x00000008U // .. .. GEM0_CPU_1XCLKACT = 0x0 // .. .. ==> 0XF800012C[6:6] = 0x00000000U // .. .. ==> MASK : 0x00000040U VAL : 0x00000000U // .. .. GEM1_CPU_1XCLKACT = 0x0 // .. .. ==> 0XF800012C[7:7] = 0x00000000U // .. .. ==> MASK : 0x00000080U VAL : 0x00000000U // .. .. SDI0_CPU_1XCLKACT = 0x1 // .. .. ==> 0XF800012C[10:10] = 0x00000001U // .. .. ==> MASK : 0x00000400U VAL : 0x00000400U // .. .. SDI1_CPU_1XCLKACT = 0x0 // .. .. ==> 0XF800012C[11:11] = 0x00000000U // .. .. ==> MASK : 0x00000800U VAL : 0x00000000U // .. .. SPI0_CPU_1XCLKACT = 0x0 // .. .. ==> 0XF800012C[14:14] = 0x00000000U // .. .. ==> MASK : 0x00004000U VAL : 0x00000000U // .. .. SPI1_CPU_1XCLKACT = 0x0 // .. .. ==> 0XF800012C[15:15] = 0x00000000U // .. .. ==> MASK : 0x00008000U VAL : 0x00000000U // .. .. CAN0_CPU_1XCLKACT = 0x0 // .. .. ==> 0XF800012C[16:16] = 0x00000000U // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U // .. .. CAN1_CPU_1XCLKACT = 0x0 // .. .. ==> 0XF800012C[17:17] = 0x00000000U // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U // .. .. I2C0_CPU_1XCLKACT = 0x1 // .. .. ==> 0XF800012C[18:18] = 0x00000001U // .. .. ==> MASK : 0x00040000U VAL : 0x00040000U // .. .. I2C1_CPU_1XCLKACT = 0x1 // .. .. ==> 0XF800012C[19:19] = 0x00000001U // .. .. ==> MASK : 0x00080000U VAL : 0x00080000U // .. .. UART0_CPU_1XCLKACT = 0x0 // .. .. ==> 0XF800012C[20:20] = 0x00000000U // .. .. ==> MASK : 0x00100000U VAL : 0x00000000U // .. .. UART1_CPU_1XCLKACT = 0x0 // .. .. ==> 0XF800012C[21:21] = 0x00000000U // .. .. ==> MASK : 0x00200000U VAL : 0x00000000U // .. .. GPIO_CPU_1XCLKACT = 0x1 // .. .. ==> 0XF800012C[22:22] = 0x00000001U // .. .. ==> MASK : 0x00400000U VAL : 0x00400000U // .. .. LQSPI_CPU_1XCLKACT = 0x0 // .. .. ==> 0XF800012C[23:23] = 0x00000000U // .. .. ==> MASK : 0x00800000U VAL : 0x00000000U // .. .. SMC_CPU_1XCLKACT = 0x1 // .. .. ==> 0XF800012C[24:24] = 0x00000001U // .. .. ==> MASK : 0x01000000U VAL : 0x01000000U // .. .. EMIT_MASKWRITE(0XF800012C, 0x01FFCCCDU ,0x014C040DU), // .. FINISH: CLOCK CONTROL SLCR REGISTERS // .. START: THIS SHOULD BE BLANK // .. FINISH: THIS SHOULD BE BLANK // .. START: LOCK IT BACK // .. LOCK_KEY = 0X767B // .. ==> 0XF8000004[15:0] = 0x0000767BU // .. ==> MASK : 0x0000FFFFU VAL : 0x0000767BU // .. EMIT_WRITE(0XF8000004, 0x0000767BU), // .. FINISH: LOCK IT BACK // FINISH: top // EMIT_EXIT(), // }; unsigned long ps7_mio_init_data_3_0[] = { // START: top // .. START: SLCR SETTINGS // .. UNLOCK_KEY = 0XDF0D // .. ==> 0XF8000008[15:0] = 0x0000DF0DU // .. ==> MASK : 0x0000FFFFU VAL : 0x0000DF0DU // .. EMIT_WRITE(0XF8000008, 0x0000DF0DU), // .. FINISH: SLCR SETTINGS // .. START: OCM REMAPPING // .. FINISH: OCM REMAPPING // .. START: MIO PROGRAMMING // .. TRI_ENABLE = 0 // .. ==> 0XF8000740[0:0] = 0x00000000U // .. ==> MASK : 0x00000001U VAL : 0x00000000U // .. L0_SEL = 0 // .. ==> 0XF8000740[1:1] = 0x00000000U // .. ==> MASK : 0x00000002U VAL : 0x00000000U // .. L1_SEL = 0 // .. ==> 0XF8000740[2:2] = 0x00000000U // .. ==> MASK : 0x00000004U VAL : 0x00000000U // .. L2_SEL = 0 // .. ==> 0XF8000740[4:3] = 0x00000000U // .. ==> MASK : 0x00000018U VAL : 0x00000000U // .. L3_SEL = 4 // .. ==> 0XF8000740[7:5] = 0x00000004U // .. ==> MASK : 0x000000E0U VAL : 0x00000080U // .. Speed = 0 // .. ==> 0XF8000740[8:8] = 0x00000000U // .. ==> MASK : 0x00000100U VAL : 0x00000000U // .. IO_Type = 1 // .. ==> 0XF8000740[11:9] = 0x00000001U // .. ==> MASK : 0x00000E00U VAL : 0x00000200U // .. PULLUP = 1 // .. ==> 0XF8000740[12:12] = 0x00000001U // .. ==> MASK : 0x00001000U VAL : 0x00001000U // .. DisableRcvr = 0 // .. ==> 0XF8000740[13:13] = 0x00000000U // .. ==> MASK : 0x00002000U VAL : 0x00000000U // .. EMIT_MASKWRITE(0XF8000740, 0x00003FFFU ,0x00001280U), // .. TRI_ENABLE = 0 // .. ==> 0XF8000744[0:0] = 0x00000000U // .. ==> MASK : 0x00000001U VAL : 0x00000000U // .. L0_SEL = 0 // .. ==> 0XF8000744[1:1] = 0x00000000U // .. ==> MASK : 0x00000002U VAL : 0x00000000U // .. L1_SEL = 0 // .. ==> 0XF8000744[2:2] = 0x00000000U // .. ==> MASK : 0x00000004U VAL : 0x00000000U // .. L2_SEL = 0 // .. ==> 0XF8000744[4:3] = 0x00000000U // .. ==> MASK : 0x00000018U VAL : 0x00000000U // .. L3_SEL = 4 // .. ==> 0XF8000744[7:5] = 0x00000004U // .. ==> MASK : 0x000000E0U VAL : 0x00000080U // .. Speed = 0 // .. ==> 0XF8000744[8:8] = 0x00000000U // .. ==> MASK : 0x00000100U VAL : 0x00000000U // .. IO_Type = 1 // .. ==> 0XF8000744[11:9] = 0x00000001U // .. ==> MASK : 0x00000E00U VAL : 0x00000200U // .. PULLUP = 1 // .. ==> 0XF8000744[12:12] = 0x00000001U // .. ==> MASK : 0x00001000U VAL : 0x00001000U // .. DisableRcvr = 0 // .. ==> 0XF8000744[13:13] = 0x00000000U // .. ==> MASK : 0x00002000U VAL : 0x00000000U // .. EMIT_MASKWRITE(0XF8000744, 0x00003FFFU ,0x00001280U), // .. TRI_ENABLE = 0 // .. ==> 0XF8000748[0:0] = 0x00000000U // .. ==> MASK : 0x00000001U VAL : 0x00000000U // .. L0_SEL = 0 // .. ==> 0XF8000748[1:1] = 0x00000000U // .. ==> MASK : 0x00000002U VAL : 0x00000000U // .. L1_SEL = 0 // .. ==> 0XF8000748[2:2] = 0x00000000U // .. ==> MASK : 0x00000004U VAL : 0x00000000U // .. L2_SEL = 0 // .. ==> 0XF8000748[4:3] = 0x00000000U // .. ==> MASK : 0x00000018U VAL : 0x00000000U // .. L3_SEL = 4 // .. ==> 0XF8000748[7:5] = 0x00000004U // .. ==> MASK : 0x000000E0U VAL : 0x00000080U // .. Speed = 0 // .. ==> 0XF8000748[8:8] = 0x00000000U // .. ==> MASK : 0x00000100U VAL : 0x00000000U // .. IO_Type = 1 // .. ==> 0XF8000748[11:9] = 0x00000001U // .. ==> MASK : 0x00000E00U VAL : 0x00000200U // .. PULLUP = 1 // .. ==> 0XF8000748[12:12] = 0x00000001U // .. ==> MASK : 0x00001000U VAL : 0x00001000U // .. DisableRcvr = 0 // .. ==> 0XF8000748[13:13] = 0x00000000U // .. ==> MASK : 0x00002000U VAL : 0x00000000U // .. EMIT_MASKWRITE(0XF8000748, 0x00003FFFU ,0x00001280U), // .. TRI_ENABLE = 0 // .. ==> 0XF800074C[0:0] = 0x00000000U // .. ==> MASK : 0x00000001U VAL : 0x00000000U // .. L0_SEL = 0 // .. ==> 0XF800074C[1:1] = 0x00000000U // .. ==> MASK : 0x00000002U VAL : 0x00000000U // .. L1_SEL = 0 // .. ==> 0XF800074C[2:2] = 0x00000000U // .. ==> MASK : 0x00000004U VAL : 0x00000000U // .. L2_SEL = 0 // .. ==> 0XF800074C[4:3] = 0x00000000U // .. ==> MASK : 0x00000018U VAL : 0x00000000U // .. L3_SEL = 4 // .. ==> 0XF800074C[7:5] = 0x00000004U // .. ==> MASK : 0x000000E0U VAL : 0x00000080U // .. Speed = 0 // .. ==> 0XF800074C[8:8] = 0x00000000U // .. ==> MASK : 0x00000100U VAL : 0x00000000U // .. IO_Type = 1 // .. ==> 0XF800074C[11:9] = 0x00000001U // .. ==> MASK : 0x00000E00U VAL : 0x00000200U // .. PULLUP = 1 // .. ==> 0XF800074C[12:12] = 0x00000001U // .. ==> MASK : 0x00001000U VAL : 0x00001000U // .. DisableRcvr = 0 // .. ==> 0XF800074C[13:13] = 0x00000000U // .. ==> MASK : 0x00002000U VAL : 0x00000000U // .. EMIT_MASKWRITE(0XF800074C, 0x00003FFFU ,0x00001280U), // .. TRI_ENABLE = 0 // .. ==> 0XF8000750[0:0] = 0x00000000U // .. ==> MASK : 0x00000001U VAL : 0x00000000U // .. L0_SEL = 0 // .. ==> 0XF8000750[1:1] = 0x00000000U // .. ==> MASK : 0x00000002U VAL : 0x00000000U // .. L1_SEL = 0 // .. ==> 0XF8000750[2:2] = 0x00000000U // .. ==> MASK : 0x00000004U VAL : 0x00000000U // .. L2_SEL = 0 // .. ==> 0XF8000750[4:3] = 0x00000000U // .. ==> MASK : 0x00000018U VAL : 0x00000000U // .. L3_SEL = 4 // .. ==> 0XF8000750[7:5] = 0x00000004U // .. ==> MASK : 0x000000E0U VAL : 0x00000080U // .. Speed = 0 // .. ==> 0XF8000750[8:8] = 0x00000000U // .. ==> MASK : 0x00000100U VAL : 0x00000000U // .. IO_Type = 1 // .. ==> 0XF8000750[11:9] = 0x00000001U // .. ==> MASK : 0x00000E00U VAL : 0x00000200U // .. PULLUP = 1 // .. ==> 0XF8000750[12:12] = 0x00000001U // .. ==> MASK : 0x00001000U VAL : 0x00001000U // .. DisableRcvr = 0 // .. ==> 0XF8000750[13:13] = 0x00000000U // .. ==> MASK : 0x00002000U VAL : 0x00000000U // .. EMIT_MASKWRITE(0XF8000750, 0x00003FFFU ,0x00001280U), // .. TRI_ENABLE = 0 // .. ==> 0XF8000754[0:0] = 0x00000000U // .. ==> MASK : 0x00000001U VAL : 0x00000000U // .. L0_SEL = 0 // .. ==> 0XF8000754[1:1] = 0x00000000U // .. ==> MASK : 0x00000002U VAL : 0x00000000U // .. L1_SEL = 0 // .. ==> 0XF8000754[2:2] = 0x00000000U // .. ==> MASK : 0x00000004U VAL : 0x00000000U // .. L2_SEL = 0 // .. ==> 0XF8000754[4:3] = 0x00000000U // .. ==> MASK : 0x00000018U VAL : 0x00000000U // .. L3_SEL = 4 // .. ==> 0XF8000754[7:5] = 0x00000004U // .. ==> MASK : 0x000000E0U VAL : 0x00000080U // .. Speed = 0 // .. ==> 0XF8000754[8:8] = 0x00000000U // .. ==> MASK : 0x00000100U VAL : 0x00000000U // .. IO_Type = 1 // .. ==> 0XF8000754[11:9] = 0x00000001U // .. ==> MASK : 0x00000E00U VAL : 0x00000200U // .. PULLUP = 1 // .. ==> 0XF8000754[12:12] = 0x00000001U // .. ==> MASK : 0x00001000U VAL : 0x00001000U // .. DisableRcvr = 0 // .. ==> 0XF8000754[13:13] = 0x00000000U // .. ==> MASK : 0x00002000U VAL : 0x00000000U // .. EMIT_MASKWRITE(0XF8000754, 0x00003FFFU ,0x00001280U), // .. SDIO0_WP_SEL = 55 // .. ==> 0XF8000830[5:0] = 0x00000037U // .. ==> MASK : 0x0000003FU VAL : 0x00000037U // .. SDIO0_CD_SEL = 56 // .. ==> 0XF8000830[21:16] = 0x00000038U // .. ==> MASK : 0x003F0000U VAL : 0x00380000U // .. EMIT_MASKWRITE(0XF8000830, 0x003F003FU ,0x00380037U), // .. FINISH: MIO PROGRAMMING // .. START: LOCK IT BACK // .. LOCK_KEY = 0X767B // .. ==> 0XF8000004[15:0] = 0x0000767BU // .. ==> MASK : 0x0000FFFFU VAL : 0x0000767BU // .. EMIT_WRITE(0XF8000004, 0x0000767BU), // .. FINISH: LOCK IT BACK // FINISH: top // EMIT_EXIT(), // }; unsigned long ps7_peripherals_init_data_3_0[] = { // START: top // .. START: SLCR SETTINGS // .. UNLOCK_KEY = 0XDF0D // .. ==> 0XF8000008[15:0] = 0x0000DF0DU // .. ==> MASK : 0x0000FFFFU VAL : 0x0000DF0DU // .. EMIT_WRITE(0XF8000008, 0x0000DF0DU), // .. FINISH: SLCR SETTINGS // .. START: LOCK IT BACK // .. LOCK_KEY = 0X767B // .. ==> 0XF8000004[15:0] = 0x0000767BU // .. ==> MASK : 0x0000FFFFU VAL : 0x0000767BU // .. EMIT_WRITE(0XF8000004, 0x0000767BU), // .. FINISH: LOCK IT BACK // .. START: SRAM/NOR SET OPMODE // .. FINISH: SRAM/NOR SET OPMODE // .. START: UART REGISTERS // .. FINISH: UART REGISTERS // .. START: QSPI REGISTERS // .. Holdb_dr = 1 // .. ==> 0XE000D000[19:19] = 0x00000001U // .. ==> MASK : 0x00080000U VAL : 0x00080000U // .. EMIT_MASKWRITE(0XE000D000, 0x00080000U ,0x00080000U), // .. FINISH: QSPI REGISTERS // .. START: PL POWER ON RESET REGISTERS // .. PCFG_POR_CNT_4K = 0 // .. ==> 0XF8007000[29:29] = 0x00000000U // .. ==> MASK : 0x20000000U VAL : 0x00000000U // .. EMIT_MASKWRITE(0XF8007000, 0x20000000U ,0x00000000U), // .. FINISH: PL POWER ON RESET REGISTERS // .. START: SMC TIMING CALCULATION REGISTER UPDATE // .. .. START: NAND SET CYCLE // .. .. FINISH: NAND SET CYCLE // .. .. START: OPMODE // .. .. FINISH: OPMODE // .. .. START: DIRECT COMMAND // .. .. FINISH: DIRECT COMMAND // .. .. START: SRAM/NOR CS0 SET CYCLE // .. .. FINISH: SRAM/NOR CS0 SET CYCLE // .. .. START: DIRECT COMMAND // .. .. FINISH: DIRECT COMMAND // .. .. START: NOR CS0 BASE ADDRESS // .. .. FINISH: NOR CS0 BASE ADDRESS // .. .. START: SRAM/NOR CS1 SET CYCLE // .. .. FINISH: SRAM/NOR CS1 SET CYCLE // .. .. START: DIRECT COMMAND // .. .. FINISH: DIRECT COMMAND // .. .. START: NOR CS1 BASE ADDRESS // .. .. FINISH: NOR CS1 BASE ADDRESS // .. .. START: USB RESET // .. .. FINISH: USB RESET // .. .. START: ENET RESET // .. .. FINISH: ENET RESET // .. .. START: I2C RESET // .. .. FINISH: I2C RESET // .. .. START: NOR CHIP SELECT // .. .. .. START: DIR MODE BANK 0 // .. .. .. FINISH: DIR MODE BANK 0 // .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] // .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] // .. .. .. START: OUTPUT ENABLE BANK 0 // .. .. .. FINISH: OUTPUT ENABLE BANK 0 // .. .. FINISH: NOR CHIP SELECT // .. FINISH: SMC TIMING CALCULATION REGISTER UPDATE // FINISH: top // EMIT_EXIT(), // }; unsigned long ps7_post_config_3_0[] = { // START: top // .. START: SLCR SETTINGS // .. UNLOCK_KEY = 0XDF0D // .. ==> 0XF8000008[15:0] = 0x0000DF0DU // .. ==> MASK : 0x0000FFFFU VAL : 0x0000DF0DU // .. EMIT_WRITE(0XF8000008, 0x0000DF0DU), // .. FINISH: SLCR SETTINGS // .. START: ENABLING LEVEL SHIFTER // .. USER_LVL_INP_EN_0 = 1 // .. ==> 0XF8000900[3:3] = 0x00000001U // .. ==> MASK : 0x00000008U VAL : 0x00000008U // .. USER_LVL_OUT_EN_0 = 1 // .. ==> 0XF8000900[2:2] = 0x00000001U // .. ==> MASK : 0x00000004U VAL : 0x00000004U // .. USER_LVL_INP_EN_1 = 1 // .. ==> 0XF8000900[1:1] = 0x00000001U // .. ==> MASK : 0x00000002U VAL : 0x00000002U // .. USER_LVL_OUT_EN_1 = 1 // .. ==> 0XF8000900[0:0] = 0x00000001U // .. ==> MASK : 0x00000001U VAL : 0x00000001U // .. EMIT_MASKWRITE(0XF8000900, 0x0000000FU ,0x0000000FU), // .. FINISH: ENABLING LEVEL SHIFTER // .. START: FPGA RESETS TO 0 // .. reserved_3 = 0 // .. ==> 0XF8000240[31:25] = 0x00000000U // .. ==> MASK : 0xFE000000U VAL : 0x00000000U // .. reserved_FPGA_ACP_RST = 0 // .. ==> 0XF8000240[24:24] = 0x00000000U // .. ==> MASK : 0x01000000U VAL : 0x00000000U // .. reserved_FPGA_AXDS3_RST = 0 // .. ==> 0XF8000240[23:23] = 0x00000000U // .. ==> MASK : 0x00800000U VAL : 0x00000000U // .. reserved_FPGA_AXDS2_RST = 0 // .. ==> 0XF8000240[22:22] = 0x00000000U // .. ==> MASK : 0x00400000U VAL : 0x00000000U // .. reserved_FPGA_AXDS1_RST = 0 // .. ==> 0XF8000240[21:21] = 0x00000000U // .. ==> MASK : 0x00200000U VAL : 0x00000000U // .. reserved_FPGA_AXDS0_RST = 0 // .. ==> 0XF8000240[20:20] = 0x00000000U // .. ==> MASK : 0x00100000U VAL : 0x00000000U // .. reserved_2 = 0 // .. ==> 0XF8000240[19:18] = 0x00000000U // .. ==> MASK : 0x000C0000U VAL : 0x00000000U // .. reserved_FSSW1_FPGA_RST = 0 // .. ==> 0XF8000240[17:17] = 0x00000000U // .. ==> MASK : 0x00020000U VAL : 0x00000000U // .. reserved_FSSW0_FPGA_RST = 0 // .. ==> 0XF8000240[16:16] = 0x00000000U // .. ==> MASK : 0x00010000U VAL : 0x00000000U // .. reserved_1 = 0 // .. ==> 0XF8000240[15:14] = 0x00000000U // .. ==> MASK : 0x0000C000U VAL : 0x00000000U // .. reserved_FPGA_FMSW1_RST = 0 // .. ==> 0XF8000240[13:13] = 0x00000000U // .. ==> MASK : 0x00002000U VAL : 0x00000000U // .. reserved_FPGA_FMSW0_RST = 0 // .. ==> 0XF8000240[12:12] = 0x00000000U // .. ==> MASK : 0x00001000U VAL : 0x00000000U // .. reserved_FPGA_DMA3_RST = 0 // .. ==> 0XF8000240[11:11] = 0x00000000U // .. ==> MASK : 0x00000800U VAL : 0x00000000U // .. reserved_FPGA_DMA2_RST = 0 // .. ==> 0XF8000240[10:10] = 0x00000000U // .. ==> MASK : 0x00000400U VAL : 0x00000000U // .. reserved_FPGA_DMA1_RST = 0 // .. ==> 0XF8000240[9:9] = 0x00000000U // .. ==> MASK : 0x00000200U VAL : 0x00000000U // .. reserved_FPGA_DMA0_RST = 0 // .. ==> 0XF8000240[8:8] = 0x00000000U // .. ==> MASK : 0x00000100U VAL : 0x00000000U // .. reserved = 0 // .. ==> 0XF8000240[7:4] = 0x00000000U // .. ==> MASK : 0x000000F0U VAL : 0x00000000U // .. FPGA3_OUT_RST = 0 // .. ==> 0XF8000240[3:3] = 0x00000000U // .. ==> MASK : 0x00000008U VAL : 0x00000000U // .. FPGA2_OUT_RST = 0 // .. ==> 0XF8000240[2:2] = 0x00000000U // .. ==> MASK : 0x00000004U VAL : 0x00000000U // .. FPGA1_OUT_RST = 0 // .. ==> 0XF8000240[1:1] = 0x00000000U // .. ==> MASK : 0x00000002U VAL : 0x00000000U // .. FPGA0_OUT_RST = 0 // .. ==> 0XF8000240[0:0] = 0x00000000U // .. ==> MASK : 0x00000001U VAL : 0x00000000U // .. EMIT_MASKWRITE(0XF8000240, 0xFFFFFFFFU ,0x00000000U), // .. FINISH: FPGA RESETS TO 0 // .. START: AFI REGISTERS // .. .. START: AFI0 REGISTERS // .. .. FINISH: AFI0 REGISTERS // .. .. START: AFI1 REGISTERS // .. .. FINISH: AFI1 REGISTERS // .. .. START: AFI2 REGISTERS // .. .. FINISH: AFI2 REGISTERS // .. .. START: AFI3 REGISTERS // .. .. FINISH: AFI3 REGISTERS // .. .. START: AFI2 SECURE REGISTER // .. .. FINISH: AFI2 SECURE REGISTER // .. FINISH: AFI REGISTERS // .. START: LOCK IT BACK // .. LOCK_KEY = 0X767B // .. ==> 0XF8000004[15:0] = 0x0000767BU // .. ==> MASK : 0x0000FFFFU VAL : 0x0000767BU // .. EMIT_WRITE(0XF8000004, 0x0000767BU), // .. FINISH: LOCK IT BACK // FINISH: top // EMIT_EXIT(), // }; unsigned long ps7_debug_3_0[] = { // START: top // .. START: CROSS TRIGGER CONFIGURATIONS // .. .. START: UNLOCKING CTI REGISTERS // .. .. KEY = 0XC5ACCE55 // .. .. ==> 0XF8898FB0[31:0] = 0xC5ACCE55U // .. .. ==> MASK : 0xFFFFFFFFU VAL : 0xC5ACCE55U // .. .. EMIT_WRITE(0XF8898FB0, 0xC5ACCE55U), // .. .. KEY = 0XC5ACCE55 // .. .. ==> 0XF8899FB0[31:0] = 0xC5ACCE55U // .. .. ==> MASK : 0xFFFFFFFFU VAL : 0xC5ACCE55U // .. .. EMIT_WRITE(0XF8899FB0, 0xC5ACCE55U), // .. .. KEY = 0XC5ACCE55 // .. .. ==> 0XF8809FB0[31:0] = 0xC5ACCE55U // .. .. ==> MASK : 0xFFFFFFFFU VAL : 0xC5ACCE55U // .. .. EMIT_WRITE(0XF8809FB0, 0xC5ACCE55U), // .. .. FINISH: UNLOCKING CTI REGISTERS // .. .. START: ENABLING CTI MODULES AND CHANNELS // .. .. FINISH: ENABLING CTI MODULES AND CHANNELS // .. .. START: MAPPING CPU0, CPU1 AND FTM EVENTS TO CTM CHANNELS // .. .. FINISH: MAPPING CPU0, CPU1 AND FTM EVENTS TO CTM CHANNELS // .. FINISH: CROSS TRIGGER CONFIGURATIONS // FINISH: top // EMIT_EXIT(), // }; unsigned long ps7_pll_init_data_2_0[] = { // START: top // .. START: SLCR SETTINGS // .. UNLOCK_KEY = 0XDF0D // .. ==> 0XF8000008[15:0] = 0x0000DF0DU // .. ==> MASK : 0x0000FFFFU VAL : 0x0000DF0DU // .. EMIT_WRITE(0XF8000008, 0x0000DF0DU), // .. FINISH: SLCR SETTINGS // .. START: PLL SLCR REGISTERS // .. .. START: ARM PLL INIT // .. .. PLL_RES = 0x2 // .. .. ==> 0XF8000110[7:4] = 0x00000002U // .. .. ==> MASK : 0x000000F0U VAL : 0x00000020U // .. .. PLL_CP = 0x2 // .. .. ==> 0XF8000110[11:8] = 0x00000002U // .. .. ==> MASK : 0x00000F00U VAL : 0x00000200U // .. .. LOCK_CNT = 0xfa // .. .. ==> 0XF8000110[21:12] = 0x000000FAU // .. .. ==> MASK : 0x003FF000U VAL : 0x000FA000U // .. .. EMIT_MASKWRITE(0XF8000110, 0x003FFFF0U ,0x000FA220U), // .. .. .. START: UPDATE FB_DIV // .. .. .. PLL_FDIV = 0x28 // .. .. .. ==> 0XF8000100[18:12] = 0x00000028U // .. .. .. ==> MASK : 0x0007F000U VAL : 0x00028000U // .. .. .. EMIT_MASKWRITE(0XF8000100, 0x0007F000U ,0x00028000U), // .. .. .. FINISH: UPDATE FB_DIV // .. .. .. START: BY PASS PLL // .. .. .. PLL_BYPASS_FORCE = 1 // .. .. .. ==> 0XF8000100[4:4] = 0x00000001U // .. .. .. ==> MASK : 0x00000010U VAL : 0x00000010U // .. .. .. EMIT_MASKWRITE(0XF8000100, 0x00000010U ,0x00000010U), // .. .. .. FINISH: BY PASS PLL // .. .. .. START: ASSERT RESET // .. .. .. PLL_RESET = 1 // .. .. .. ==> 0XF8000100[0:0] = 0x00000001U // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000001U // .. .. .. EMIT_MASKWRITE(0XF8000100, 0x00000001U ,0x00000001U), // .. .. .. FINISH: ASSERT RESET // .. .. .. START: DEASSERT RESET // .. .. .. PLL_RESET = 0 // .. .. .. ==> 0XF8000100[0:0] = 0x00000000U // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000000U // .. .. .. EMIT_MASKWRITE(0XF8000100, 0x00000001U ,0x00000000U), // .. .. .. FINISH: DEASSERT RESET // .. .. .. START: CHECK PLL STATUS // .. .. .. ARM_PLL_LOCK = 1 // .. .. .. ==> 0XF800010C[0:0] = 0x00000001U // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000001U // .. .. .. EMIT_MASKPOLL(0XF800010C, 0x00000001U), // .. .. .. FINISH: CHECK PLL STATUS // .. .. .. START: REMOVE PLL BY PASS // .. .. .. PLL_BYPASS_FORCE = 0 // .. .. .. ==> 0XF8000100[4:4] = 0x00000000U // .. .. .. ==> MASK : 0x00000010U VAL : 0x00000000U // .. .. .. EMIT_MASKWRITE(0XF8000100, 0x00000010U ,0x00000000U), // .. .. .. FINISH: REMOVE PLL BY PASS // .. .. .. SRCSEL = 0x0 // .. .. .. ==> 0XF8000120[5:4] = 0x00000000U // .. .. .. ==> MASK : 0x00000030U VAL : 0x00000000U // .. .. .. DIVISOR = 0x2 // .. .. .. ==> 0XF8000120[13:8] = 0x00000002U // .. .. .. ==> MASK : 0x00003F00U VAL : 0x00000200U // .. .. .. CPU_6OR4XCLKACT = 0x1 // .. .. .. ==> 0XF8000120[24:24] = 0x00000001U // .. .. .. ==> MASK : 0x01000000U VAL : 0x01000000U // .. .. .. CPU_3OR2XCLKACT = 0x1 // .. .. .. ==> 0XF8000120[25:25] = 0x00000001U // .. .. .. ==> MASK : 0x02000000U VAL : 0x02000000U // .. .. .. CPU_2XCLKACT = 0x1 // .. .. .. ==> 0XF8000120[26:26] = 0x00000001U // .. .. .. ==> MASK : 0x04000000U VAL : 0x04000000U // .. .. .. CPU_1XCLKACT = 0x1 // .. .. .. ==> 0XF8000120[27:27] = 0x00000001U // .. .. .. ==> MASK : 0x08000000U VAL : 0x08000000U // .. .. .. CPU_PERI_CLKACT = 0x1 // .. .. .. ==> 0XF8000120[28:28] = 0x00000001U // .. .. .. ==> MASK : 0x10000000U VAL : 0x10000000U // .. .. .. EMIT_MASKWRITE(0XF8000120, 0x1F003F30U ,0x1F000200U), // .. .. FINISH: ARM PLL INIT // .. .. START: DDR PLL INIT // .. .. PLL_RES = 0x2 // .. .. ==> 0XF8000114[7:4] = 0x00000002U // .. .. ==> MASK : 0x000000F0U VAL : 0x00000020U // .. .. PLL_CP = 0x2 // .. .. ==> 0XF8000114[11:8] = 0x00000002U // .. .. ==> MASK : 0x00000F00U VAL : 0x00000200U // .. .. LOCK_CNT = 0x12c // .. .. ==> 0XF8000114[21:12] = 0x0000012CU // .. .. ==> MASK : 0x003FF000U VAL : 0x0012C000U // .. .. EMIT_MASKWRITE(0XF8000114, 0x003FFFF0U ,0x0012C220U), // .. .. .. START: UPDATE FB_DIV // .. .. .. PLL_FDIV = 0x20 // .. .. .. ==> 0XF8000104[18:12] = 0x00000020U // .. .. .. ==> MASK : 0x0007F000U VAL : 0x00020000U // .. .. .. EMIT_MASKWRITE(0XF8000104, 0x0007F000U ,0x00020000U), // .. .. .. FINISH: UPDATE FB_DIV // .. .. .. START: BY PASS PLL // .. .. .. PLL_BYPASS_FORCE = 1 // .. .. .. ==> 0XF8000104[4:4] = 0x00000001U // .. .. .. ==> MASK : 0x00000010U VAL : 0x00000010U // .. .. .. EMIT_MASKWRITE(0XF8000104, 0x00000010U ,0x00000010U), // .. .. .. FINISH: BY PASS PLL // .. .. .. START: ASSERT RESET // .. .. .. PLL_RESET = 1 // .. .. .. ==> 0XF8000104[0:0] = 0x00000001U // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000001U // .. .. .. EMIT_MASKWRITE(0XF8000104, 0x00000001U ,0x00000001U), // .. .. .. FINISH: ASSERT RESET // .. .. .. START: DEASSERT RESET // .. .. .. PLL_RESET = 0 // .. .. .. ==> 0XF8000104[0:0] = 0x00000000U // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000000U // .. .. .. EMIT_MASKWRITE(0XF8000104, 0x00000001U ,0x00000000U), // .. .. .. FINISH: DEASSERT RESET // .. .. .. START: CHECK PLL STATUS // .. .. .. DDR_PLL_LOCK = 1 // .. .. .. ==> 0XF800010C[1:1] = 0x00000001U // .. .. .. ==> MASK : 0x00000002U VAL : 0x00000002U // .. .. .. EMIT_MASKPOLL(0XF800010C, 0x00000002U), // .. .. .. FINISH: CHECK PLL STATUS // .. .. .. START: REMOVE PLL BY PASS // .. .. .. PLL_BYPASS_FORCE = 0 // .. .. .. ==> 0XF8000104[4:4] = 0x00000000U // .. .. .. ==> MASK : 0x00000010U VAL : 0x00000000U // .. .. .. EMIT_MASKWRITE(0XF8000104, 0x00000010U ,0x00000000U), // .. .. .. FINISH: REMOVE PLL BY PASS // .. .. .. DDR_3XCLKACT = 0x1 // .. .. .. ==> 0XF8000124[0:0] = 0x00000001U // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000001U // .. .. .. DDR_2XCLKACT = 0x1 // .. .. .. ==> 0XF8000124[1:1] = 0x00000001U // .. .. .. ==> MASK : 0x00000002U VAL : 0x00000002U // .. .. .. DDR_3XCLK_DIVISOR = 0x2 // .. .. .. ==> 0XF8000124[25:20] = 0x00000002U // .. .. .. ==> MASK : 0x03F00000U VAL : 0x00200000U // .. .. .. DDR_2XCLK_DIVISOR = 0x3 // .. .. .. ==> 0XF8000124[31:26] = 0x00000003U // .. .. .. ==> MASK : 0xFC000000U VAL : 0x0C000000U // .. .. .. EMIT_MASKWRITE(0XF8000124, 0xFFF00003U ,0x0C200003U), // .. .. FINISH: DDR PLL INIT // .. .. START: IO PLL INIT // .. .. PLL_RES = 0x4 // .. .. ==> 0XF8000118[7:4] = 0x00000004U // .. .. ==> MASK : 0x000000F0U VAL : 0x00000040U // .. .. PLL_CP = 0x2 // .. .. ==> 0XF8000118[11:8] = 0x00000002U // .. .. ==> MASK : 0x00000F00U VAL : 0x00000200U // .. .. LOCK_CNT = 0xfa // .. .. ==> 0XF8000118[21:12] = 0x000000FAU // .. .. ==> MASK : 0x003FF000U VAL : 0x000FA000U // .. .. EMIT_MASKWRITE(0XF8000118, 0x003FFFF0U ,0x000FA240U), // .. .. .. START: UPDATE FB_DIV // .. .. .. PLL_FDIV = 0x30 // .. .. .. ==> 0XF8000108[18:12] = 0x00000030U // .. .. .. ==> MASK : 0x0007F000U VAL : 0x00030000U // .. .. .. EMIT_MASKWRITE(0XF8000108, 0x0007F000U ,0x00030000U), // .. .. .. FINISH: UPDATE FB_DIV // .. .. .. START: BY PASS PLL // .. .. .. PLL_BYPASS_FORCE = 1 // .. .. .. ==> 0XF8000108[4:4] = 0x00000001U // .. .. .. ==> MASK : 0x00000010U VAL : 0x00000010U // .. .. .. EMIT_MASKWRITE(0XF8000108, 0x00000010U ,0x00000010U), // .. .. .. FINISH: BY PASS PLL // .. .. .. START: ASSERT RESET // .. .. .. PLL_RESET = 1 // .. .. .. ==> 0XF8000108[0:0] = 0x00000001U // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000001U // .. .. .. EMIT_MASKWRITE(0XF8000108, 0x00000001U ,0x00000001U), // .. .. .. FINISH: ASSERT RESET // .. .. .. START: DEASSERT RESET // .. .. .. PLL_RESET = 0 // .. .. .. ==> 0XF8000108[0:0] = 0x00000000U // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000000U // .. .. .. EMIT_MASKWRITE(0XF8000108, 0x00000001U ,0x00000000U), // .. .. .. FINISH: DEASSERT RESET // .. .. .. START: CHECK PLL STATUS // .. .. .. IO_PLL_LOCK = 1 // .. .. .. ==> 0XF800010C[2:2] = 0x00000001U // .. .. .. ==> MASK : 0x00000004U VAL : 0x00000004U // .. .. .. EMIT_MASKPOLL(0XF800010C, 0x00000004U), // .. .. .. FINISH: CHECK PLL STATUS // .. .. .. START: REMOVE PLL BY PASS // .. .. .. PLL_BYPASS_FORCE = 0 // .. .. .. ==> 0XF8000108[4:4] = 0x00000000U // .. .. .. ==> MASK : 0x00000010U VAL : 0x00000000U // .. .. .. EMIT_MASKWRITE(0XF8000108, 0x00000010U ,0x00000000U), // .. .. .. FINISH: REMOVE PLL BY PASS // .. .. FINISH: IO PLL INIT // .. FINISH: PLL SLCR REGISTERS // .. START: LOCK IT BACK // .. LOCK_KEY = 0X767B // .. ==> 0XF8000004[15:0] = 0x0000767BU // .. ==> MASK : 0x0000FFFFU VAL : 0x0000767BU // .. EMIT_WRITE(0XF8000004, 0x0000767BU), // .. FINISH: LOCK IT BACK // FINISH: top // EMIT_EXIT(), // }; unsigned long ps7_clock_init_data_2_0[] = { // START: top // .. START: SLCR SETTINGS // .. UNLOCK_KEY = 0XDF0D // .. ==> 0XF8000008[15:0] = 0x0000DF0DU // .. ==> MASK : 0x0000FFFFU VAL : 0x0000DF0DU // .. EMIT_WRITE(0XF8000008, 0x0000DF0DU), // .. FINISH: SLCR SETTINGS // .. START: CLOCK CONTROL SLCR REGISTERS // .. CLKACT = 0x1 // .. ==> 0XF8000128[0:0] = 0x00000001U // .. ==> MASK : 0x00000001U VAL : 0x00000001U // .. DIVISOR0 = 0xf // .. ==> 0XF8000128[13:8] = 0x0000000FU // .. ==> MASK : 0x00003F00U VAL : 0x00000F00U // .. DIVISOR1 = 0x7 // .. ==> 0XF8000128[25:20] = 0x00000007U // .. ==> MASK : 0x03F00000U VAL : 0x00700000U // .. EMIT_MASKWRITE(0XF8000128, 0x03F03F01U ,0x00700F01U), // .. CLKACT0 = 0x1 // .. ==> 0XF8000150[0:0] = 0x00000001U // .. ==> MASK : 0x00000001U VAL : 0x00000001U // .. CLKACT1 = 0x0 // .. ==> 0XF8000150[1:1] = 0x00000000U // .. ==> MASK : 0x00000002U VAL : 0x00000000U // .. SRCSEL = 0x0 // .. ==> 0XF8000150[5:4] = 0x00000000U // .. ==> MASK : 0x00000030U VAL : 0x00000000U // .. DIVISOR = 0x10 // .. ==> 0XF8000150[13:8] = 0x00000010U // .. ==> MASK : 0x00003F00U VAL : 0x00001000U // .. EMIT_MASKWRITE(0XF8000150, 0x00003F33U ,0x00001001U), // .. .. START: TRACE CLOCK // .. .. FINISH: TRACE CLOCK // .. .. CLKACT = 0x1 // .. .. ==> 0XF8000168[0:0] = 0x00000001U // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U // .. .. SRCSEL = 0x0 // .. .. ==> 0XF8000168[5:4] = 0x00000000U // .. .. ==> MASK : 0x00000030U VAL : 0x00000000U // .. .. DIVISOR = 0x8 // .. .. ==> 0XF8000168[13:8] = 0x00000008U // .. .. ==> MASK : 0x00003F00U VAL : 0x00000800U // .. .. EMIT_MASKWRITE(0XF8000168, 0x00003F31U ,0x00000801U), // .. .. SRCSEL = 0x0 // .. .. ==> 0XF8000170[5:4] = 0x00000000U // .. .. ==> MASK : 0x00000030U VAL : 0x00000000U // .. .. DIVISOR0 = 0x8 // .. .. ==> 0XF8000170[13:8] = 0x00000008U // .. .. ==> MASK : 0x00003F00U VAL : 0x00000800U // .. .. DIVISOR1 = 0x4 // .. .. ==> 0XF8000170[25:20] = 0x00000004U // .. .. ==> MASK : 0x03F00000U VAL : 0x00400000U // .. .. EMIT_MASKWRITE(0XF8000170, 0x03F03F30U ,0x00400800U), // .. .. SRCSEL = 0x0 // .. .. ==> 0XF8000180[5:4] = 0x00000000U // .. .. ==> MASK : 0x00000030U VAL : 0x00000000U // .. .. DIVISOR0 = 0x8 // .. .. ==> 0XF8000180[13:8] = 0x00000008U // .. .. ==> MASK : 0x00003F00U VAL : 0x00000800U // .. .. DIVISOR1 = 0x4 // .. .. ==> 0XF8000180[25:20] = 0x00000004U // .. .. ==> MASK : 0x03F00000U VAL : 0x00400000U // .. .. EMIT_MASKWRITE(0XF8000180, 0x03F03F30U ,0x00400800U), // .. .. SRCSEL = 0x0 // .. .. ==> 0XF8000190[5:4] = 0x00000000U // .. .. ==> MASK : 0x00000030U VAL : 0x00000000U // .. .. DIVISOR0 = 0x8 // .. .. ==> 0XF8000190[13:8] = 0x00000008U // .. .. ==> MASK : 0x00003F00U VAL : 0x00000800U // .. .. DIVISOR1 = 0x4 // .. .. ==> 0XF8000190[25:20] = 0x00000004U // .. .. ==> MASK : 0x03F00000U VAL : 0x00400000U // .. .. EMIT_MASKWRITE(0XF8000190, 0x03F03F30U ,0x00400800U), // .. .. SRCSEL = 0x0 // .. .. ==> 0XF80001A0[5:4] = 0x00000000U // .. .. ==> MASK : 0x00000030U VAL : 0x00000000U // .. .. DIVISOR0 = 0x8 // .. .. ==> 0XF80001A0[13:8] = 0x00000008U // .. .. ==> MASK : 0x00003F00U VAL : 0x00000800U // .. .. DIVISOR1 = 0x4 // .. .. ==> 0XF80001A0[25:20] = 0x00000004U // .. .. ==> MASK : 0x03F00000U VAL : 0x00400000U // .. .. EMIT_MASKWRITE(0XF80001A0, 0x03F03F30U ,0x00400800U), // .. .. CLK_621_TRUE = 0x1 // .. .. ==> 0XF80001C4[0:0] = 0x00000001U // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U // .. .. EMIT_MASKWRITE(0XF80001C4, 0x00000001U ,0x00000001U), // .. .. DMA_CPU_2XCLKACT = 0x1 // .. .. ==> 0XF800012C[0:0] = 0x00000001U // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U // .. .. USB0_CPU_1XCLKACT = 0x1 // .. .. ==> 0XF800012C[2:2] = 0x00000001U // .. .. ==> MASK : 0x00000004U VAL : 0x00000004U // .. .. USB1_CPU_1XCLKACT = 0x1 // .. .. ==> 0XF800012C[3:3] = 0x00000001U // .. .. ==> MASK : 0x00000008U VAL : 0x00000008U // .. .. GEM0_CPU_1XCLKACT = 0x0 // .. .. ==> 0XF800012C[6:6] = 0x00000000U // .. .. ==> MASK : 0x00000040U VAL : 0x00000000U // .. .. GEM1_CPU_1XCLKACT = 0x0 // .. .. ==> 0XF800012C[7:7] = 0x00000000U // .. .. ==> MASK : 0x00000080U VAL : 0x00000000U // .. .. SDI0_CPU_1XCLKACT = 0x1 // .. .. ==> 0XF800012C[10:10] = 0x00000001U // .. .. ==> MASK : 0x00000400U VAL : 0x00000400U // .. .. SDI1_CPU_1XCLKACT = 0x0 // .. .. ==> 0XF800012C[11:11] = 0x00000000U // .. .. ==> MASK : 0x00000800U VAL : 0x00000000U // .. .. SPI0_CPU_1XCLKACT = 0x0 // .. .. ==> 0XF800012C[14:14] = 0x00000000U // .. .. ==> MASK : 0x00004000U VAL : 0x00000000U // .. .. SPI1_CPU_1XCLKACT = 0x0 // .. .. ==> 0XF800012C[15:15] = 0x00000000U // .. .. ==> MASK : 0x00008000U VAL : 0x00000000U // .. .. CAN0_CPU_1XCLKACT = 0x0 // .. .. ==> 0XF800012C[16:16] = 0x00000000U // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U // .. .. CAN1_CPU_1XCLKACT = 0x0 // .. .. ==> 0XF800012C[17:17] = 0x00000000U // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U // .. .. I2C0_CPU_1XCLKACT = 0x1 // .. .. ==> 0XF800012C[18:18] = 0x00000001U // .. .. ==> MASK : 0x00040000U VAL : 0x00040000U // .. .. I2C1_CPU_1XCLKACT = 0x1 // .. .. ==> 0XF800012C[19:19] = 0x00000001U // .. .. ==> MASK : 0x00080000U VAL : 0x00080000U // .. .. UART0_CPU_1XCLKACT = 0x0 // .. .. ==> 0XF800012C[20:20] = 0x00000000U // .. .. ==> MASK : 0x00100000U VAL : 0x00000000U // .. .. UART1_CPU_1XCLKACT = 0x0 // .. .. ==> 0XF800012C[21:21] = 0x00000000U // .. .. ==> MASK : 0x00200000U VAL : 0x00000000U // .. .. GPIO_CPU_1XCLKACT = 0x1 // .. .. ==> 0XF800012C[22:22] = 0x00000001U // .. .. ==> MASK : 0x00400000U VAL : 0x00400000U // .. .. LQSPI_CPU_1XCLKACT = 0x0 // .. .. ==> 0XF800012C[23:23] = 0x00000000U // .. .. ==> MASK : 0x00800000U VAL : 0x00000000U // .. .. SMC_CPU_1XCLKACT = 0x1 // .. .. ==> 0XF800012C[24:24] = 0x00000001U // .. .. ==> MASK : 0x01000000U VAL : 0x01000000U // .. .. EMIT_MASKWRITE(0XF800012C, 0x01FFCCCDU ,0x014C040DU), // .. FINISH: CLOCK CONTROL SLCR REGISTERS // .. START: THIS SHOULD BE BLANK // .. FINISH: THIS SHOULD BE BLANK // .. START: LOCK IT BACK // .. LOCK_KEY = 0X767B // .. ==> 0XF8000004[15:0] = 0x0000767BU // .. ==> MASK : 0x0000FFFFU VAL : 0x0000767BU // .. EMIT_WRITE(0XF8000004, 0x0000767BU), // .. FINISH: LOCK IT BACK // FINISH: top // EMIT_EXIT(), // }; unsigned long ps7_mio_init_data_2_0[] = { // START: top // .. START: SLCR SETTINGS // .. UNLOCK_KEY = 0XDF0D // .. ==> 0XF8000008[15:0] = 0x0000DF0DU // .. ==> MASK : 0x0000FFFFU VAL : 0x0000DF0DU // .. EMIT_WRITE(0XF8000008, 0x0000DF0DU), // .. FINISH: SLCR SETTINGS // .. START: OCM REMAPPING // .. FINISH: OCM REMAPPING // .. START: MIO PROGRAMMING // .. TRI_ENABLE = 0 // .. ==> 0XF8000740[0:0] = 0x00000000U // .. ==> MASK : 0x00000001U VAL : 0x00000000U // .. L0_SEL = 0 // .. ==> 0XF8000740[1:1] = 0x00000000U // .. ==> MASK : 0x00000002U VAL : 0x00000000U // .. L1_SEL = 0 // .. ==> 0XF8000740[2:2] = 0x00000000U // .. ==> MASK : 0x00000004U VAL : 0x00000000U // .. L2_SEL = 0 // .. ==> 0XF8000740[4:3] = 0x00000000U // .. ==> MASK : 0x00000018U VAL : 0x00000000U // .. L3_SEL = 4 // .. ==> 0XF8000740[7:5] = 0x00000004U // .. ==> MASK : 0x000000E0U VAL : 0x00000080U // .. Speed = 0 // .. ==> 0XF8000740[8:8] = 0x00000000U // .. ==> MASK : 0x00000100U VAL : 0x00000000U // .. IO_Type = 1 // .. ==> 0XF8000740[11:9] = 0x00000001U // .. ==> MASK : 0x00000E00U VAL : 0x00000200U // .. PULLUP = 1 // .. ==> 0XF8000740[12:12] = 0x00000001U // .. ==> MASK : 0x00001000U VAL : 0x00001000U // .. DisableRcvr = 0 // .. ==> 0XF8000740[13:13] = 0x00000000U // .. ==> MASK : 0x00002000U VAL : 0x00000000U // .. EMIT_MASKWRITE(0XF8000740, 0x00003FFFU ,0x00001280U), // .. TRI_ENABLE = 0 // .. ==> 0XF8000744[0:0] = 0x00000000U // .. ==> MASK : 0x00000001U VAL : 0x00000000U // .. L0_SEL = 0 // .. ==> 0XF8000744[1:1] = 0x00000000U // .. ==> MASK : 0x00000002U VAL : 0x00000000U // .. L1_SEL = 0 // .. ==> 0XF8000744[2:2] = 0x00000000U // .. ==> MASK : 0x00000004U VAL : 0x00000000U // .. L2_SEL = 0 // .. ==> 0XF8000744[4:3] = 0x00000000U // .. ==> MASK : 0x00000018U VAL : 0x00000000U // .. L3_SEL = 4 // .. ==> 0XF8000744[7:5] = 0x00000004U // .. ==> MASK : 0x000000E0U VAL : 0x00000080U // .. Speed = 0 // .. ==> 0XF8000744[8:8] = 0x00000000U // .. ==> MASK : 0x00000100U VAL : 0x00000000U // .. IO_Type = 1 // .. ==> 0XF8000744[11:9] = 0x00000001U // .. ==> MASK : 0x00000E00U VAL : 0x00000200U // .. PULLUP = 1 // .. ==> 0XF8000744[12:12] = 0x00000001U // .. ==> MASK : 0x00001000U VAL : 0x00001000U // .. DisableRcvr = 0 // .. ==> 0XF8000744[13:13] = 0x00000000U // .. ==> MASK : 0x00002000U VAL : 0x00000000U // .. EMIT_MASKWRITE(0XF8000744, 0x00003FFFU ,0x00001280U), // .. TRI_ENABLE = 0 // .. ==> 0XF8000748[0:0] = 0x00000000U // .. ==> MASK : 0x00000001U VAL : 0x00000000U // .. L0_SEL = 0 // .. ==> 0XF8000748[1:1] = 0x00000000U // .. ==> MASK : 0x00000002U VAL : 0x00000000U // .. L1_SEL = 0 // .. ==> 0XF8000748[2:2] = 0x00000000U // .. ==> MASK : 0x00000004U VAL : 0x00000000U // .. L2_SEL = 0 // .. ==> 0XF8000748[4:3] = 0x00000000U // .. ==> MASK : 0x00000018U VAL : 0x00000000U // .. L3_SEL = 4 // .. ==> 0XF8000748[7:5] = 0x00000004U // .. ==> MASK : 0x000000E0U VAL : 0x00000080U // .. Speed = 0 // .. ==> 0XF8000748[8:8] = 0x00000000U // .. ==> MASK : 0x00000100U VAL : 0x00000000U // .. IO_Type = 1 // .. ==> 0XF8000748[11:9] = 0x00000001U // .. ==> MASK : 0x00000E00U VAL : 0x00000200U // .. PULLUP = 1 // .. ==> 0XF8000748[12:12] = 0x00000001U // .. ==> MASK : 0x00001000U VAL : 0x00001000U // .. DisableRcvr = 0 // .. ==> 0XF8000748[13:13] = 0x00000000U // .. ==> MASK : 0x00002000U VAL : 0x00000000U // .. EMIT_MASKWRITE(0XF8000748, 0x00003FFFU ,0x00001280U), // .. TRI_ENABLE = 0 // .. ==> 0XF800074C[0:0] = 0x00000000U // .. ==> MASK : 0x00000001U VAL : 0x00000000U // .. L0_SEL = 0 // .. ==> 0XF800074C[1:1] = 0x00000000U // .. ==> MASK : 0x00000002U VAL : 0x00000000U // .. L1_SEL = 0 // .. ==> 0XF800074C[2:2] = 0x00000000U // .. ==> MASK : 0x00000004U VAL : 0x00000000U // .. L2_SEL = 0 // .. ==> 0XF800074C[4:3] = 0x00000000U // .. ==> MASK : 0x00000018U VAL : 0x00000000U // .. L3_SEL = 4 // .. ==> 0XF800074C[7:5] = 0x00000004U // .. ==> MASK : 0x000000E0U VAL : 0x00000080U // .. Speed = 0 // .. ==> 0XF800074C[8:8] = 0x00000000U // .. ==> MASK : 0x00000100U VAL : 0x00000000U // .. IO_Type = 1 // .. ==> 0XF800074C[11:9] = 0x00000001U // .. ==> MASK : 0x00000E00U VAL : 0x00000200U // .. PULLUP = 1 // .. ==> 0XF800074C[12:12] = 0x00000001U // .. ==> MASK : 0x00001000U VAL : 0x00001000U // .. DisableRcvr = 0 // .. ==> 0XF800074C[13:13] = 0x00000000U // .. ==> MASK : 0x00002000U VAL : 0x00000000U // .. EMIT_MASKWRITE(0XF800074C, 0x00003FFFU ,0x00001280U), // .. TRI_ENABLE = 0 // .. ==> 0XF8000750[0:0] = 0x00000000U // .. ==> MASK : 0x00000001U VAL : 0x00000000U // .. L0_SEL = 0 // .. ==> 0XF8000750[1:1] = 0x00000000U // .. ==> MASK : 0x00000002U VAL : 0x00000000U // .. L1_SEL = 0 // .. ==> 0XF8000750[2:2] = 0x00000000U // .. ==> MASK : 0x00000004U VAL : 0x00000000U // .. L2_SEL = 0 // .. ==> 0XF8000750[4:3] = 0x00000000U // .. ==> MASK : 0x00000018U VAL : 0x00000000U // .. L3_SEL = 4 // .. ==> 0XF8000750[7:5] = 0x00000004U // .. ==> MASK : 0x000000E0U VAL : 0x00000080U // .. Speed = 0 // .. ==> 0XF8000750[8:8] = 0x00000000U // .. ==> MASK : 0x00000100U VAL : 0x00000000U // .. IO_Type = 1 // .. ==> 0XF8000750[11:9] = 0x00000001U // .. ==> MASK : 0x00000E00U VAL : 0x00000200U // .. PULLUP = 1 // .. ==> 0XF8000750[12:12] = 0x00000001U // .. ==> MASK : 0x00001000U VAL : 0x00001000U // .. DisableRcvr = 0 // .. ==> 0XF8000750[13:13] = 0x00000000U // .. ==> MASK : 0x00002000U VAL : 0x00000000U // .. EMIT_MASKWRITE(0XF8000750, 0x00003FFFU ,0x00001280U), // .. TRI_ENABLE = 0 // .. ==> 0XF8000754[0:0] = 0x00000000U // .. ==> MASK : 0x00000001U VAL : 0x00000000U // .. L0_SEL = 0 // .. ==> 0XF8000754[1:1] = 0x00000000U // .. ==> MASK : 0x00000002U VAL : 0x00000000U // .. L1_SEL = 0 // .. ==> 0XF8000754[2:2] = 0x00000000U // .. ==> MASK : 0x00000004U VAL : 0x00000000U // .. L2_SEL = 0 // .. ==> 0XF8000754[4:3] = 0x00000000U // .. ==> MASK : 0x00000018U VAL : 0x00000000U // .. L3_SEL = 4 // .. ==> 0XF8000754[7:5] = 0x00000004U // .. ==> MASK : 0x000000E0U VAL : 0x00000080U // .. Speed = 0 // .. ==> 0XF8000754[8:8] = 0x00000000U // .. ==> MASK : 0x00000100U VAL : 0x00000000U // .. IO_Type = 1 // .. ==> 0XF8000754[11:9] = 0x00000001U // .. ==> MASK : 0x00000E00U VAL : 0x00000200U // .. PULLUP = 1 // .. ==> 0XF8000754[12:12] = 0x00000001U // .. ==> MASK : 0x00001000U VAL : 0x00001000U // .. DisableRcvr = 0 // .. ==> 0XF8000754[13:13] = 0x00000000U // .. ==> MASK : 0x00002000U VAL : 0x00000000U // .. EMIT_MASKWRITE(0XF8000754, 0x00003FFFU ,0x00001280U), // .. SDIO0_WP_SEL = 55 // .. ==> 0XF8000830[5:0] = 0x00000037U // .. ==> MASK : 0x0000003FU VAL : 0x00000037U // .. SDIO0_CD_SEL = 56 // .. ==> 0XF8000830[21:16] = 0x00000038U // .. ==> MASK : 0x003F0000U VAL : 0x00380000U // .. EMIT_MASKWRITE(0XF8000830, 0x003F003FU ,0x00380037U), // .. FINISH: MIO PROGRAMMING // .. START: LOCK IT BACK // .. LOCK_KEY = 0X767B // .. ==> 0XF8000004[15:0] = 0x0000767BU // .. ==> MASK : 0x0000FFFFU VAL : 0x0000767BU // .. EMIT_WRITE(0XF8000004, 0x0000767BU), // .. FINISH: LOCK IT BACK // FINISH: top // EMIT_EXIT(), // }; unsigned long ps7_peripherals_init_data_2_0[] = { // START: top // .. START: SLCR SETTINGS // .. UNLOCK_KEY = 0XDF0D // .. ==> 0XF8000008[15:0] = 0x0000DF0DU // .. ==> MASK : 0x0000FFFFU VAL : 0x0000DF0DU // .. EMIT_WRITE(0XF8000008, 0x0000DF0DU), // .. FINISH: SLCR SETTINGS // .. START: LOCK IT BACK // .. LOCK_KEY = 0X767B // .. ==> 0XF8000004[15:0] = 0x0000767BU // .. ==> MASK : 0x0000FFFFU VAL : 0x0000767BU // .. EMIT_WRITE(0XF8000004, 0x0000767BU), // .. FINISH: LOCK IT BACK // .. START: SRAM/NOR SET OPMODE // .. FINISH: SRAM/NOR SET OPMODE // .. START: UART REGISTERS // .. FINISH: UART REGISTERS // .. START: QSPI REGISTERS // .. Holdb_dr = 1 // .. ==> 0XE000D000[19:19] = 0x00000001U // .. ==> MASK : 0x00080000U VAL : 0x00080000U // .. EMIT_MASKWRITE(0XE000D000, 0x00080000U ,0x00080000U), // .. FINISH: QSPI REGISTERS // .. START: PL POWER ON RESET REGISTERS // .. PCFG_POR_CNT_4K = 0 // .. ==> 0XF8007000[29:29] = 0x00000000U // .. ==> MASK : 0x20000000U VAL : 0x00000000U // .. EMIT_MASKWRITE(0XF8007000, 0x20000000U ,0x00000000U), // .. FINISH: PL POWER ON RESET REGISTERS // .. START: SMC TIMING CALCULATION REGISTER UPDATE // .. .. START: NAND SET CYCLE // .. .. FINISH: NAND SET CYCLE // .. .. START: OPMODE // .. .. FINISH: OPMODE // .. .. START: DIRECT COMMAND // .. .. FINISH: DIRECT COMMAND // .. .. START: SRAM/NOR CS0 SET CYCLE // .. .. FINISH: SRAM/NOR CS0 SET CYCLE // .. .. START: DIRECT COMMAND // .. .. FINISH: DIRECT COMMAND // .. .. START: NOR CS0 BASE ADDRESS // .. .. FINISH: NOR CS0 BASE ADDRESS // .. .. START: SRAM/NOR CS1 SET CYCLE // .. .. FINISH: SRAM/NOR CS1 SET CYCLE // .. .. START: DIRECT COMMAND // .. .. FINISH: DIRECT COMMAND // .. .. START: NOR CS1 BASE ADDRESS // .. .. FINISH: NOR CS1 BASE ADDRESS // .. .. START: USB RESET // .. .. FINISH: USB RESET // .. .. START: ENET RESET // .. .. FINISH: ENET RESET // .. .. START: I2C RESET // .. .. FINISH: I2C RESET // .. .. START: NOR CHIP SELECT // .. .. .. START: DIR MODE BANK 0 // .. .. .. FINISH: DIR MODE BANK 0 // .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] // .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] // .. .. .. START: OUTPUT ENABLE BANK 0 // .. .. .. FINISH: OUTPUT ENABLE BANK 0 // .. .. FINISH: NOR CHIP SELECT // .. FINISH: SMC TIMING CALCULATION REGISTER UPDATE // FINISH: top // EMIT_EXIT(), // }; unsigned long ps7_post_config_2_0[] = { // START: top // .. START: SLCR SETTINGS // .. UNLOCK_KEY = 0XDF0D // .. ==> 0XF8000008[15:0] = 0x0000DF0DU // .. ==> MASK : 0x0000FFFFU VAL : 0x0000DF0DU // .. EMIT_WRITE(0XF8000008, 0x0000DF0DU), // .. FINISH: SLCR SETTINGS // .. START: ENABLING LEVEL SHIFTER // .. USER_INP_ICT_EN_0 = 3 // .. ==> 0XF8000900[1:0] = 0x00000003U // .. ==> MASK : 0x00000003U VAL : 0x00000003U // .. USER_INP_ICT_EN_1 = 3 // .. ==> 0XF8000900[3:2] = 0x00000003U // .. ==> MASK : 0x0000000CU VAL : 0x0000000CU // .. EMIT_MASKWRITE(0XF8000900, 0x0000000FU ,0x0000000FU), // .. FINISH: ENABLING LEVEL SHIFTER // .. START: FPGA RESETS TO 0 // .. reserved_3 = 0 // .. ==> 0XF8000240[31:25] = 0x00000000U // .. ==> MASK : 0xFE000000U VAL : 0x00000000U // .. FPGA_ACP_RST = 0 // .. ==> 0XF8000240[24:24] = 0x00000000U // .. ==> MASK : 0x01000000U VAL : 0x00000000U // .. FPGA_AXDS3_RST = 0 // .. ==> 0XF8000240[23:23] = 0x00000000U // .. ==> MASK : 0x00800000U VAL : 0x00000000U // .. FPGA_AXDS2_RST = 0 // .. ==> 0XF8000240[22:22] = 0x00000000U // .. ==> MASK : 0x00400000U VAL : 0x00000000U // .. FPGA_AXDS1_RST = 0 // .. ==> 0XF8000240[21:21] = 0x00000000U // .. ==> MASK : 0x00200000U VAL : 0x00000000U // .. FPGA_AXDS0_RST = 0 // .. ==> 0XF8000240[20:20] = 0x00000000U // .. ==> MASK : 0x00100000U VAL : 0x00000000U // .. reserved_2 = 0 // .. ==> 0XF8000240[19:18] = 0x00000000U // .. ==> MASK : 0x000C0000U VAL : 0x00000000U // .. FSSW1_FPGA_RST = 0 // .. ==> 0XF8000240[17:17] = 0x00000000U // .. ==> MASK : 0x00020000U VAL : 0x00000000U // .. FSSW0_FPGA_RST = 0 // .. ==> 0XF8000240[16:16] = 0x00000000U // .. ==> MASK : 0x00010000U VAL : 0x00000000U // .. reserved_1 = 0 // .. ==> 0XF8000240[15:14] = 0x00000000U // .. ==> MASK : 0x0000C000U VAL : 0x00000000U // .. FPGA_FMSW1_RST = 0 // .. ==> 0XF8000240[13:13] = 0x00000000U // .. ==> MASK : 0x00002000U VAL : 0x00000000U // .. FPGA_FMSW0_RST = 0 // .. ==> 0XF8000240[12:12] = 0x00000000U // .. ==> MASK : 0x00001000U VAL : 0x00000000U // .. FPGA_DMA3_RST = 0 // .. ==> 0XF8000240[11:11] = 0x00000000U // .. ==> MASK : 0x00000800U VAL : 0x00000000U // .. FPGA_DMA2_RST = 0 // .. ==> 0XF8000240[10:10] = 0x00000000U // .. ==> MASK : 0x00000400U VAL : 0x00000000U // .. FPGA_DMA1_RST = 0 // .. ==> 0XF8000240[9:9] = 0x00000000U // .. ==> MASK : 0x00000200U VAL : 0x00000000U // .. FPGA_DMA0_RST = 0 // .. ==> 0XF8000240[8:8] = 0x00000000U // .. ==> MASK : 0x00000100U VAL : 0x00000000U // .. reserved = 0 // .. ==> 0XF8000240[7:4] = 0x00000000U // .. ==> MASK : 0x000000F0U VAL : 0x00000000U // .. FPGA3_OUT_RST = 0 // .. ==> 0XF8000240[3:3] = 0x00000000U // .. ==> MASK : 0x00000008U VAL : 0x00000000U // .. FPGA2_OUT_RST = 0 // .. ==> 0XF8000240[2:2] = 0x00000000U // .. ==> MASK : 0x00000004U VAL : 0x00000000U // .. FPGA1_OUT_RST = 0 // .. ==> 0XF8000240[1:1] = 0x00000000U // .. ==> MASK : 0x00000002U VAL : 0x00000000U // .. FPGA0_OUT_RST = 0 // .. ==> 0XF8000240[0:0] = 0x00000000U // .. ==> MASK : 0x00000001U VAL : 0x00000000U // .. EMIT_MASKWRITE(0XF8000240, 0xFFFFFFFFU ,0x00000000U), // .. FINISH: FPGA RESETS TO 0 // .. START: AFI REGISTERS // .. .. START: AFI0 REGISTERS // .. .. FINISH: AFI0 REGISTERS // .. .. START: AFI1 REGISTERS // .. .. FINISH: AFI1 REGISTERS // .. .. START: AFI2 REGISTERS // .. .. FINISH: AFI2 REGISTERS // .. .. START: AFI3 REGISTERS // .. .. FINISH: AFI3 REGISTERS // .. FINISH: AFI REGISTERS // .. START: LOCK IT BACK // .. LOCK_KEY = 0X767B // .. ==> 0XF8000004[15:0] = 0x0000767BU // .. ==> MASK : 0x0000FFFFU VAL : 0x0000767BU // .. EMIT_WRITE(0XF8000004, 0x0000767BU), // .. FINISH: LOCK IT BACK // FINISH: top // EMIT_EXIT(), // }; unsigned long ps7_debug_2_0[] = { // START: top // .. START: CROSS TRIGGER CONFIGURATIONS // .. .. START: UNLOCKING CTI REGISTERS // .. .. KEY = 0XC5ACCE55 // .. .. ==> 0XF8898FB0[31:0] = 0xC5ACCE55U // .. .. ==> MASK : 0xFFFFFFFFU VAL : 0xC5ACCE55U // .. .. EMIT_WRITE(0XF8898FB0, 0xC5ACCE55U), // .. .. KEY = 0XC5ACCE55 // .. .. ==> 0XF8899FB0[31:0] = 0xC5ACCE55U // .. .. ==> MASK : 0xFFFFFFFFU VAL : 0xC5ACCE55U // .. .. EMIT_WRITE(0XF8899FB0, 0xC5ACCE55U), // .. .. KEY = 0XC5ACCE55 // .. .. ==> 0XF8809FB0[31:0] = 0xC5ACCE55U // .. .. ==> MASK : 0xFFFFFFFFU VAL : 0xC5ACCE55U // .. .. EMIT_WRITE(0XF8809FB0, 0xC5ACCE55U), // .. .. FINISH: UNLOCKING CTI REGISTERS // .. .. START: ENABLING CTI MODULES AND CHANNELS // .. .. FINISH: ENABLING CTI MODULES AND CHANNELS // .. .. START: MAPPING CPU0, CPU1 AND FTM EVENTS TO CTM CHANNELS // .. .. FINISH: MAPPING CPU0, CPU1 AND FTM EVENTS TO CTM CHANNELS // .. FINISH: CROSS TRIGGER CONFIGURATIONS // FINISH: top // EMIT_EXIT(), // }; unsigned long ps7_pll_init_data_1_0[] = { // START: top // .. START: SLCR SETTINGS // .. UNLOCK_KEY = 0XDF0D // .. ==> 0XF8000008[15:0] = 0x0000DF0DU // .. ==> MASK : 0x0000FFFFU VAL : 0x0000DF0DU // .. EMIT_WRITE(0XF8000008, 0x0000DF0DU), // .. FINISH: SLCR SETTINGS // .. START: PLL SLCR REGISTERS // .. .. START: ARM PLL INIT // .. .. PLL_RES = 0x2 // .. .. ==> 0XF8000110[7:4] = 0x00000002U // .. .. ==> MASK : 0x000000F0U VAL : 0x00000020U // .. .. PLL_CP = 0x2 // .. .. ==> 0XF8000110[11:8] = 0x00000002U // .. .. ==> MASK : 0x00000F00U VAL : 0x00000200U // .. .. LOCK_CNT = 0xfa // .. .. ==> 0XF8000110[21:12] = 0x000000FAU // .. .. ==> MASK : 0x003FF000U VAL : 0x000FA000U // .. .. EMIT_MASKWRITE(0XF8000110, 0x003FFFF0U ,0x000FA220U), // .. .. .. START: UPDATE FB_DIV // .. .. .. PLL_FDIV = 0x28 // .. .. .. ==> 0XF8000100[18:12] = 0x00000028U // .. .. .. ==> MASK : 0x0007F000U VAL : 0x00028000U // .. .. .. EMIT_MASKWRITE(0XF8000100, 0x0007F000U ,0x00028000U), // .. .. .. FINISH: UPDATE FB_DIV // .. .. .. START: BY PASS PLL // .. .. .. PLL_BYPASS_FORCE = 1 // .. .. .. ==> 0XF8000100[4:4] = 0x00000001U // .. .. .. ==> MASK : 0x00000010U VAL : 0x00000010U // .. .. .. EMIT_MASKWRITE(0XF8000100, 0x00000010U ,0x00000010U), // .. .. .. FINISH: BY PASS PLL // .. .. .. START: ASSERT RESET // .. .. .. PLL_RESET = 1 // .. .. .. ==> 0XF8000100[0:0] = 0x00000001U // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000001U // .. .. .. EMIT_MASKWRITE(0XF8000100, 0x00000001U ,0x00000001U), // .. .. .. FINISH: ASSERT RESET // .. .. .. START: DEASSERT RESET // .. .. .. PLL_RESET = 0 // .. .. .. ==> 0XF8000100[0:0] = 0x00000000U // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000000U // .. .. .. EMIT_MASKWRITE(0XF8000100, 0x00000001U ,0x00000000U), // .. .. .. FINISH: DEASSERT RESET // .. .. .. START: CHECK PLL STATUS // .. .. .. ARM_PLL_LOCK = 1 // .. .. .. ==> 0XF800010C[0:0] = 0x00000001U // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000001U // .. .. .. EMIT_MASKPOLL(0XF800010C, 0x00000001U), // .. .. .. FINISH: CHECK PLL STATUS // .. .. .. START: REMOVE PLL BY PASS // .. .. .. PLL_BYPASS_FORCE = 0 // .. .. .. ==> 0XF8000100[4:4] = 0x00000000U // .. .. .. ==> MASK : 0x00000010U VAL : 0x00000000U // .. .. .. EMIT_MASKWRITE(0XF8000100, 0x00000010U ,0x00000000U), // .. .. .. FINISH: REMOVE PLL BY PASS // .. .. .. SRCSEL = 0x0 // .. .. .. ==> 0XF8000120[5:4] = 0x00000000U // .. .. .. ==> MASK : 0x00000030U VAL : 0x00000000U // .. .. .. DIVISOR = 0x2 // .. .. .. ==> 0XF8000120[13:8] = 0x00000002U // .. .. .. ==> MASK : 0x00003F00U VAL : 0x00000200U // .. .. .. CPU_6OR4XCLKACT = 0x1 // .. .. .. ==> 0XF8000120[24:24] = 0x00000001U // .. .. .. ==> MASK : 0x01000000U VAL : 0x01000000U // .. .. .. CPU_3OR2XCLKACT = 0x1 // .. .. .. ==> 0XF8000120[25:25] = 0x00000001U // .. .. .. ==> MASK : 0x02000000U VAL : 0x02000000U // .. .. .. CPU_2XCLKACT = 0x1 // .. .. .. ==> 0XF8000120[26:26] = 0x00000001U // .. .. .. ==> MASK : 0x04000000U VAL : 0x04000000U // .. .. .. CPU_1XCLKACT = 0x1 // .. .. .. ==> 0XF8000120[27:27] = 0x00000001U // .. .. .. ==> MASK : 0x08000000U VAL : 0x08000000U // .. .. .. CPU_PERI_CLKACT = 0x1 // .. .. .. ==> 0XF8000120[28:28] = 0x00000001U // .. .. .. ==> MASK : 0x10000000U VAL : 0x10000000U // .. .. .. EMIT_MASKWRITE(0XF8000120, 0x1F003F30U ,0x1F000200U), // .. .. FINISH: ARM PLL INIT // .. .. START: DDR PLL INIT // .. .. PLL_RES = 0x2 // .. .. ==> 0XF8000114[7:4] = 0x00000002U // .. .. ==> MASK : 0x000000F0U VAL : 0x00000020U // .. .. PLL_CP = 0x2 // .. .. ==> 0XF8000114[11:8] = 0x00000002U // .. .. ==> MASK : 0x00000F00U VAL : 0x00000200U // .. .. LOCK_CNT = 0x12c // .. .. ==> 0XF8000114[21:12] = 0x0000012CU // .. .. ==> MASK : 0x003FF000U VAL : 0x0012C000U // .. .. EMIT_MASKWRITE(0XF8000114, 0x003FFFF0U ,0x0012C220U), // .. .. .. START: UPDATE FB_DIV // .. .. .. PLL_FDIV = 0x20 // .. .. .. ==> 0XF8000104[18:12] = 0x00000020U // .. .. .. ==> MASK : 0x0007F000U VAL : 0x00020000U // .. .. .. EMIT_MASKWRITE(0XF8000104, 0x0007F000U ,0x00020000U), // .. .. .. FINISH: UPDATE FB_DIV // .. .. .. START: BY PASS PLL // .. .. .. PLL_BYPASS_FORCE = 1 // .. .. .. ==> 0XF8000104[4:4] = 0x00000001U // .. .. .. ==> MASK : 0x00000010U VAL : 0x00000010U // .. .. .. EMIT_MASKWRITE(0XF8000104, 0x00000010U ,0x00000010U), // .. .. .. FINISH: BY PASS PLL // .. .. .. START: ASSERT RESET // .. .. .. PLL_RESET = 1 // .. .. .. ==> 0XF8000104[0:0] = 0x00000001U // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000001U // .. .. .. EMIT_MASKWRITE(0XF8000104, 0x00000001U ,0x00000001U), // .. .. .. FINISH: ASSERT RESET // .. .. .. START: DEASSERT RESET // .. .. .. PLL_RESET = 0 // .. .. .. ==> 0XF8000104[0:0] = 0x00000000U // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000000U // .. .. .. EMIT_MASKWRITE(0XF8000104, 0x00000001U ,0x00000000U), // .. .. .. FINISH: DEASSERT RESET // .. .. .. START: CHECK PLL STATUS // .. .. .. DDR_PLL_LOCK = 1 // .. .. .. ==> 0XF800010C[1:1] = 0x00000001U // .. .. .. ==> MASK : 0x00000002U VAL : 0x00000002U // .. .. .. EMIT_MASKPOLL(0XF800010C, 0x00000002U), // .. .. .. FINISH: CHECK PLL STATUS // .. .. .. START: REMOVE PLL BY PASS // .. .. .. PLL_BYPASS_FORCE = 0 // .. .. .. ==> 0XF8000104[4:4] = 0x00000000U // .. .. .. ==> MASK : 0x00000010U VAL : 0x00000000U // .. .. .. EMIT_MASKWRITE(0XF8000104, 0x00000010U ,0x00000000U), // .. .. .. FINISH: REMOVE PLL BY PASS // .. .. .. DDR_3XCLKACT = 0x1 // .. .. .. ==> 0XF8000124[0:0] = 0x00000001U // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000001U // .. .. .. DDR_2XCLKACT = 0x1 // .. .. .. ==> 0XF8000124[1:1] = 0x00000001U // .. .. .. ==> MASK : 0x00000002U VAL : 0x00000002U // .. .. .. DDR_3XCLK_DIVISOR = 0x2 // .. .. .. ==> 0XF8000124[25:20] = 0x00000002U // .. .. .. ==> MASK : 0x03F00000U VAL : 0x00200000U // .. .. .. DDR_2XCLK_DIVISOR = 0x3 // .. .. .. ==> 0XF8000124[31:26] = 0x00000003U // .. .. .. ==> MASK : 0xFC000000U VAL : 0x0C000000U // .. .. .. EMIT_MASKWRITE(0XF8000124, 0xFFF00003U ,0x0C200003U), // .. .. FINISH: DDR PLL INIT // .. .. START: IO PLL INIT // .. .. PLL_RES = 0x4 // .. .. ==> 0XF8000118[7:4] = 0x00000004U // .. .. ==> MASK : 0x000000F0U VAL : 0x00000040U // .. .. PLL_CP = 0x2 // .. .. ==> 0XF8000118[11:8] = 0x00000002U // .. .. ==> MASK : 0x00000F00U VAL : 0x00000200U // .. .. LOCK_CNT = 0xfa // .. .. ==> 0XF8000118[21:12] = 0x000000FAU // .. .. ==> MASK : 0x003FF000U VAL : 0x000FA000U // .. .. EMIT_MASKWRITE(0XF8000118, 0x003FFFF0U ,0x000FA240U), // .. .. .. START: UPDATE FB_DIV // .. .. .. PLL_FDIV = 0x30 // .. .. .. ==> 0XF8000108[18:12] = 0x00000030U // .. .. .. ==> MASK : 0x0007F000U VAL : 0x00030000U // .. .. .. EMIT_MASKWRITE(0XF8000108, 0x0007F000U ,0x00030000U), // .. .. .. FINISH: UPDATE FB_DIV // .. .. .. START: BY PASS PLL // .. .. .. PLL_BYPASS_FORCE = 1 // .. .. .. ==> 0XF8000108[4:4] = 0x00000001U // .. .. .. ==> MASK : 0x00000010U VAL : 0x00000010U // .. .. .. EMIT_MASKWRITE(0XF8000108, 0x00000010U ,0x00000010U), // .. .. .. FINISH: BY PASS PLL // .. .. .. START: ASSERT RESET // .. .. .. PLL_RESET = 1 // .. .. .. ==> 0XF8000108[0:0] = 0x00000001U // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000001U // .. .. .. EMIT_MASKWRITE(0XF8000108, 0x00000001U ,0x00000001U), // .. .. .. FINISH: ASSERT RESET // .. .. .. START: DEASSERT RESET // .. .. .. PLL_RESET = 0 // .. .. .. ==> 0XF8000108[0:0] = 0x00000000U // .. .. .. ==> MASK : 0x00000001U VAL : 0x00000000U // .. .. .. EMIT_MASKWRITE(0XF8000108, 0x00000001U ,0x00000000U), // .. .. .. FINISH: DEASSERT RESET // .. .. .. START: CHECK PLL STATUS // .. .. .. IO_PLL_LOCK = 1 // .. .. .. ==> 0XF800010C[2:2] = 0x00000001U // .. .. .. ==> MASK : 0x00000004U VAL : 0x00000004U // .. .. .. EMIT_MASKPOLL(0XF800010C, 0x00000004U), // .. .. .. FINISH: CHECK PLL STATUS // .. .. .. START: REMOVE PLL BY PASS // .. .. .. PLL_BYPASS_FORCE = 0 // .. .. .. ==> 0XF8000108[4:4] = 0x00000000U // .. .. .. ==> MASK : 0x00000010U VAL : 0x00000000U // .. .. .. EMIT_MASKWRITE(0XF8000108, 0x00000010U ,0x00000000U), // .. .. .. FINISH: REMOVE PLL BY PASS // .. .. FINISH: IO PLL INIT // .. FINISH: PLL SLCR REGISTERS // .. START: LOCK IT BACK // .. LOCK_KEY = 0X767B // .. ==> 0XF8000004[15:0] = 0x0000767BU // .. ==> MASK : 0x0000FFFFU VAL : 0x0000767BU // .. EMIT_WRITE(0XF8000004, 0x0000767BU), // .. FINISH: LOCK IT BACK // FINISH: top // EMIT_EXIT(), // }; unsigned long ps7_clock_init_data_1_0[] = { // START: top // .. START: SLCR SETTINGS // .. UNLOCK_KEY = 0XDF0D // .. ==> 0XF8000008[15:0] = 0x0000DF0DU // .. ==> MASK : 0x0000FFFFU VAL : 0x0000DF0DU // .. EMIT_WRITE(0XF8000008, 0x0000DF0DU), // .. FINISH: SLCR SETTINGS // .. START: CLOCK CONTROL SLCR REGISTERS // .. CLKACT = 0x1 // .. ==> 0XF8000128[0:0] = 0x00000001U // .. ==> MASK : 0x00000001U VAL : 0x00000001U // .. DIVISOR0 = 0xf // .. ==> 0XF8000128[13:8] = 0x0000000FU // .. ==> MASK : 0x00003F00U VAL : 0x00000F00U // .. DIVISOR1 = 0x7 // .. ==> 0XF8000128[25:20] = 0x00000007U // .. ==> MASK : 0x03F00000U VAL : 0x00700000U // .. EMIT_MASKWRITE(0XF8000128, 0x03F03F01U ,0x00700F01U), // .. CLKACT0 = 0x1 // .. ==> 0XF8000150[0:0] = 0x00000001U // .. ==> MASK : 0x00000001U VAL : 0x00000001U // .. CLKACT1 = 0x0 // .. ==> 0XF8000150[1:1] = 0x00000000U // .. ==> MASK : 0x00000002U VAL : 0x00000000U // .. SRCSEL = 0x0 // .. ==> 0XF8000150[5:4] = 0x00000000U // .. ==> MASK : 0x00000030U VAL : 0x00000000U // .. DIVISOR = 0x10 // .. ==> 0XF8000150[13:8] = 0x00000010U // .. ==> MASK : 0x00003F00U VAL : 0x00001000U // .. EMIT_MASKWRITE(0XF8000150, 0x00003F33U ,0x00001001U), // .. .. START: TRACE CLOCK // .. .. FINISH: TRACE CLOCK // .. .. CLKACT = 0x1 // .. .. ==> 0XF8000168[0:0] = 0x00000001U // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U // .. .. SRCSEL = 0x0 // .. .. ==> 0XF8000168[5:4] = 0x00000000U // .. .. ==> MASK : 0x00000030U VAL : 0x00000000U // .. .. DIVISOR = 0x8 // .. .. ==> 0XF8000168[13:8] = 0x00000008U // .. .. ==> MASK : 0x00003F00U VAL : 0x00000800U // .. .. EMIT_MASKWRITE(0XF8000168, 0x00003F31U ,0x00000801U), // .. .. SRCSEL = 0x0 // .. .. ==> 0XF8000170[5:4] = 0x00000000U // .. .. ==> MASK : 0x00000030U VAL : 0x00000000U // .. .. DIVISOR0 = 0x8 // .. .. ==> 0XF8000170[13:8] = 0x00000008U // .. .. ==> MASK : 0x00003F00U VAL : 0x00000800U // .. .. DIVISOR1 = 0x4 // .. .. ==> 0XF8000170[25:20] = 0x00000004U // .. .. ==> MASK : 0x03F00000U VAL : 0x00400000U // .. .. EMIT_MASKWRITE(0XF8000170, 0x03F03F30U ,0x00400800U), // .. .. SRCSEL = 0x0 // .. .. ==> 0XF8000180[5:4] = 0x00000000U // .. .. ==> MASK : 0x00000030U VAL : 0x00000000U // .. .. DIVISOR0 = 0x8 // .. .. ==> 0XF8000180[13:8] = 0x00000008U // .. .. ==> MASK : 0x00003F00U VAL : 0x00000800U // .. .. DIVISOR1 = 0x4 // .. .. ==> 0XF8000180[25:20] = 0x00000004U // .. .. ==> MASK : 0x03F00000U VAL : 0x00400000U // .. .. EMIT_MASKWRITE(0XF8000180, 0x03F03F30U ,0x00400800U), // .. .. SRCSEL = 0x0 // .. .. ==> 0XF8000190[5:4] = 0x00000000U // .. .. ==> MASK : 0x00000030U VAL : 0x00000000U // .. .. DIVISOR0 = 0x8 // .. .. ==> 0XF8000190[13:8] = 0x00000008U // .. .. ==> MASK : 0x00003F00U VAL : 0x00000800U // .. .. DIVISOR1 = 0x4 // .. .. ==> 0XF8000190[25:20] = 0x00000004U // .. .. ==> MASK : 0x03F00000U VAL : 0x00400000U // .. .. EMIT_MASKWRITE(0XF8000190, 0x03F03F30U ,0x00400800U), // .. .. SRCSEL = 0x0 // .. .. ==> 0XF80001A0[5:4] = 0x00000000U // .. .. ==> MASK : 0x00000030U VAL : 0x00000000U // .. .. DIVISOR0 = 0x8 // .. .. ==> 0XF80001A0[13:8] = 0x00000008U // .. .. ==> MASK : 0x00003F00U VAL : 0x00000800U // .. .. DIVISOR1 = 0x4 // .. .. ==> 0XF80001A0[25:20] = 0x00000004U // .. .. ==> MASK : 0x03F00000U VAL : 0x00400000U // .. .. EMIT_MASKWRITE(0XF80001A0, 0x03F03F30U ,0x00400800U), // .. .. CLK_621_TRUE = 0x1 // .. .. ==> 0XF80001C4[0:0] = 0x00000001U // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U // .. .. EMIT_MASKWRITE(0XF80001C4, 0x00000001U ,0x00000001U), // .. .. DMA_CPU_2XCLKACT = 0x1 // .. .. ==> 0XF800012C[0:0] = 0x00000001U // .. .. ==> MASK : 0x00000001U VAL : 0x00000001U // .. .. USB0_CPU_1XCLKACT = 0x1 // .. .. ==> 0XF800012C[2:2] = 0x00000001U // .. .. ==> MASK : 0x00000004U VAL : 0x00000004U // .. .. USB1_CPU_1XCLKACT = 0x1 // .. .. ==> 0XF800012C[3:3] = 0x00000001U // .. .. ==> MASK : 0x00000008U VAL : 0x00000008U // .. .. GEM0_CPU_1XCLKACT = 0x0 // .. .. ==> 0XF800012C[6:6] = 0x00000000U // .. .. ==> MASK : 0x00000040U VAL : 0x00000000U // .. .. GEM1_CPU_1XCLKACT = 0x0 // .. .. ==> 0XF800012C[7:7] = 0x00000000U // .. .. ==> MASK : 0x00000080U VAL : 0x00000000U // .. .. SDI0_CPU_1XCLKACT = 0x1 // .. .. ==> 0XF800012C[10:10] = 0x00000001U // .. .. ==> MASK : 0x00000400U VAL : 0x00000400U // .. .. SDI1_CPU_1XCLKACT = 0x0 // .. .. ==> 0XF800012C[11:11] = 0x00000000U // .. .. ==> MASK : 0x00000800U VAL : 0x00000000U // .. .. SPI0_CPU_1XCLKACT = 0x0 // .. .. ==> 0XF800012C[14:14] = 0x00000000U // .. .. ==> MASK : 0x00004000U VAL : 0x00000000U // .. .. SPI1_CPU_1XCLKACT = 0x0 // .. .. ==> 0XF800012C[15:15] = 0x00000000U // .. .. ==> MASK : 0x00008000U VAL : 0x00000000U // .. .. CAN0_CPU_1XCLKACT = 0x0 // .. .. ==> 0XF800012C[16:16] = 0x00000000U // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U // .. .. CAN1_CPU_1XCLKACT = 0x0 // .. .. ==> 0XF800012C[17:17] = 0x00000000U // .. .. ==> MASK : 0x00020000U VAL : 0x00000000U // .. .. I2C0_CPU_1XCLKACT = 0x1 // .. .. ==> 0XF800012C[18:18] = 0x00000001U // .. .. ==> MASK : 0x00040000U VAL : 0x00040000U // .. .. I2C1_CPU_1XCLKACT = 0x1 // .. .. ==> 0XF800012C[19:19] = 0x00000001U // .. .. ==> MASK : 0x00080000U VAL : 0x00080000U // .. .. UART0_CPU_1XCLKACT = 0x0 // .. .. ==> 0XF800012C[20:20] = 0x00000000U // .. .. ==> MASK : 0x00100000U VAL : 0x00000000U // .. .. UART1_CPU_1XCLKACT = 0x0 // .. .. ==> 0XF800012C[21:21] = 0x00000000U // .. .. ==> MASK : 0x00200000U VAL : 0x00000000U // .. .. GPIO_CPU_1XCLKACT = 0x1 // .. .. ==> 0XF800012C[22:22] = 0x00000001U // .. .. ==> MASK : 0x00400000U VAL : 0x00400000U // .. .. LQSPI_CPU_1XCLKACT = 0x0 // .. .. ==> 0XF800012C[23:23] = 0x00000000U // .. .. ==> MASK : 0x00800000U VAL : 0x00000000U // .. .. SMC_CPU_1XCLKACT = 0x1 // .. .. ==> 0XF800012C[24:24] = 0x00000001U // .. .. ==> MASK : 0x01000000U VAL : 0x01000000U // .. .. EMIT_MASKWRITE(0XF800012C, 0x01FFCCCDU ,0x014C040DU), // .. FINISH: CLOCK CONTROL SLCR REGISTERS // .. START: THIS SHOULD BE BLANK // .. FINISH: THIS SHOULD BE BLANK // .. START: LOCK IT BACK // .. LOCK_KEY = 0X767B // .. ==> 0XF8000004[15:0] = 0x0000767BU // .. ==> MASK : 0x0000FFFFU VAL : 0x0000767BU // .. EMIT_WRITE(0XF8000004, 0x0000767BU), // .. FINISH: LOCK IT BACK // FINISH: top // EMIT_EXIT(), // }; unsigned long ps7_mio_init_data_1_0[] = { // START: top // .. START: SLCR SETTINGS // .. UNLOCK_KEY = 0XDF0D // .. ==> 0XF8000008[15:0] = 0x0000DF0DU // .. ==> MASK : 0x0000FFFFU VAL : 0x0000DF0DU // .. EMIT_WRITE(0XF8000008, 0x0000DF0DU), // .. FINISH: SLCR SETTINGS // .. START: OCM REMAPPING // .. FINISH: OCM REMAPPING // .. START: MIO PROGRAMMING // .. TRI_ENABLE = 0 // .. ==> 0XF8000740[0:0] = 0x00000000U // .. ==> MASK : 0x00000001U VAL : 0x00000000U // .. L0_SEL = 0 // .. ==> 0XF8000740[1:1] = 0x00000000U // .. ==> MASK : 0x00000002U VAL : 0x00000000U // .. L1_SEL = 0 // .. ==> 0XF8000740[2:2] = 0x00000000U // .. ==> MASK : 0x00000004U VAL : 0x00000000U // .. L2_SEL = 0 // .. ==> 0XF8000740[4:3] = 0x00000000U // .. ==> MASK : 0x00000018U VAL : 0x00000000U // .. L3_SEL = 4 // .. ==> 0XF8000740[7:5] = 0x00000004U // .. ==> MASK : 0x000000E0U VAL : 0x00000080U // .. Speed = 0 // .. ==> 0XF8000740[8:8] = 0x00000000U // .. ==> MASK : 0x00000100U VAL : 0x00000000U // .. IO_Type = 1 // .. ==> 0XF8000740[11:9] = 0x00000001U // .. ==> MASK : 0x00000E00U VAL : 0x00000200U // .. PULLUP = 1 // .. ==> 0XF8000740[12:12] = 0x00000001U // .. ==> MASK : 0x00001000U VAL : 0x00001000U // .. DisableRcvr = 0 // .. ==> 0XF8000740[13:13] = 0x00000000U // .. ==> MASK : 0x00002000U VAL : 0x00000000U // .. EMIT_MASKWRITE(0XF8000740, 0x00003FFFU ,0x00001280U), // .. TRI_ENABLE = 0 // .. ==> 0XF8000744[0:0] = 0x00000000U // .. ==> MASK : 0x00000001U VAL : 0x00000000U // .. L0_SEL = 0 // .. ==> 0XF8000744[1:1] = 0x00000000U // .. ==> MASK : 0x00000002U VAL : 0x00000000U // .. L1_SEL = 0 // .. ==> 0XF8000744[2:2] = 0x00000000U // .. ==> MASK : 0x00000004U VAL : 0x00000000U // .. L2_SEL = 0 // .. ==> 0XF8000744[4:3] = 0x00000000U // .. ==> MASK : 0x00000018U VAL : 0x00000000U // .. L3_SEL = 4 // .. ==> 0XF8000744[7:5] = 0x00000004U // .. ==> MASK : 0x000000E0U VAL : 0x00000080U // .. Speed = 0 // .. ==> 0XF8000744[8:8] = 0x00000000U // .. ==> MASK : 0x00000100U VAL : 0x00000000U // .. IO_Type = 1 // .. ==> 0XF8000744[11:9] = 0x00000001U // .. ==> MASK : 0x00000E00U VAL : 0x00000200U // .. PULLUP = 1 // .. ==> 0XF8000744[12:12] = 0x00000001U // .. ==> MASK : 0x00001000U VAL : 0x00001000U // .. DisableRcvr = 0 // .. ==> 0XF8000744[13:13] = 0x00000000U // .. ==> MASK : 0x00002000U VAL : 0x00000000U // .. EMIT_MASKWRITE(0XF8000744, 0x00003FFFU ,0x00001280U), // .. TRI_ENABLE = 0 // .. ==> 0XF8000748[0:0] = 0x00000000U // .. ==> MASK : 0x00000001U VAL : 0x00000000U // .. L0_SEL = 0 // .. ==> 0XF8000748[1:1] = 0x00000000U // .. ==> MASK : 0x00000002U VAL : 0x00000000U // .. L1_SEL = 0 // .. ==> 0XF8000748[2:2] = 0x00000000U // .. ==> MASK : 0x00000004U VAL : 0x00000000U // .. L2_SEL = 0 // .. ==> 0XF8000748[4:3] = 0x00000000U // .. ==> MASK : 0x00000018U VAL : 0x00000000U // .. L3_SEL = 4 // .. ==> 0XF8000748[7:5] = 0x00000004U // .. ==> MASK : 0x000000E0U VAL : 0x00000080U // .. Speed = 0 // .. ==> 0XF8000748[8:8] = 0x00000000U // .. ==> MASK : 0x00000100U VAL : 0x00000000U // .. IO_Type = 1 // .. ==> 0XF8000748[11:9] = 0x00000001U // .. ==> MASK : 0x00000E00U VAL : 0x00000200U // .. PULLUP = 1 // .. ==> 0XF8000748[12:12] = 0x00000001U // .. ==> MASK : 0x00001000U VAL : 0x00001000U // .. DisableRcvr = 0 // .. ==> 0XF8000748[13:13] = 0x00000000U // .. ==> MASK : 0x00002000U VAL : 0x00000000U // .. EMIT_MASKWRITE(0XF8000748, 0x00003FFFU ,0x00001280U), // .. TRI_ENABLE = 0 // .. ==> 0XF800074C[0:0] = 0x00000000U // .. ==> MASK : 0x00000001U VAL : 0x00000000U // .. L0_SEL = 0 // .. ==> 0XF800074C[1:1] = 0x00000000U // .. ==> MASK : 0x00000002U VAL : 0x00000000U // .. L1_SEL = 0 // .. ==> 0XF800074C[2:2] = 0x00000000U // .. ==> MASK : 0x00000004U VAL : 0x00000000U // .. L2_SEL = 0 // .. ==> 0XF800074C[4:3] = 0x00000000U // .. ==> MASK : 0x00000018U VAL : 0x00000000U // .. L3_SEL = 4 // .. ==> 0XF800074C[7:5] = 0x00000004U // .. ==> MASK : 0x000000E0U VAL : 0x00000080U // .. Speed = 0 // .. ==> 0XF800074C[8:8] = 0x00000000U // .. ==> MASK : 0x00000100U VAL : 0x00000000U // .. IO_Type = 1 // .. ==> 0XF800074C[11:9] = 0x00000001U // .. ==> MASK : 0x00000E00U VAL : 0x00000200U // .. PULLUP = 1 // .. ==> 0XF800074C[12:12] = 0x00000001U // .. ==> MASK : 0x00001000U VAL : 0x00001000U // .. DisableRcvr = 0 // .. ==> 0XF800074C[13:13] = 0x00000000U // .. ==> MASK : 0x00002000U VAL : 0x00000000U // .. EMIT_MASKWRITE(0XF800074C, 0x00003FFFU ,0x00001280U), // .. TRI_ENABLE = 0 // .. ==> 0XF8000750[0:0] = 0x00000000U // .. ==> MASK : 0x00000001U VAL : 0x00000000U // .. L0_SEL = 0 // .. ==> 0XF8000750[1:1] = 0x00000000U // .. ==> MASK : 0x00000002U VAL : 0x00000000U // .. L1_SEL = 0 // .. ==> 0XF8000750[2:2] = 0x00000000U // .. ==> MASK : 0x00000004U VAL : 0x00000000U // .. L2_SEL = 0 // .. ==> 0XF8000750[4:3] = 0x00000000U // .. ==> MASK : 0x00000018U VAL : 0x00000000U // .. L3_SEL = 4 // .. ==> 0XF8000750[7:5] = 0x00000004U // .. ==> MASK : 0x000000E0U VAL : 0x00000080U // .. Speed = 0 // .. ==> 0XF8000750[8:8] = 0x00000000U // .. ==> MASK : 0x00000100U VAL : 0x00000000U // .. IO_Type = 1 // .. ==> 0XF8000750[11:9] = 0x00000001U // .. ==> MASK : 0x00000E00U VAL : 0x00000200U // .. PULLUP = 1 // .. ==> 0XF8000750[12:12] = 0x00000001U // .. ==> MASK : 0x00001000U VAL : 0x00001000U // .. DisableRcvr = 0 // .. ==> 0XF8000750[13:13] = 0x00000000U // .. ==> MASK : 0x00002000U VAL : 0x00000000U // .. EMIT_MASKWRITE(0XF8000750, 0x00003FFFU ,0x00001280U), // .. TRI_ENABLE = 0 // .. ==> 0XF8000754[0:0] = 0x00000000U // .. ==> MASK : 0x00000001U VAL : 0x00000000U // .. L0_SEL = 0 // .. ==> 0XF8000754[1:1] = 0x00000000U // .. ==> MASK : 0x00000002U VAL : 0x00000000U // .. L1_SEL = 0 // .. ==> 0XF8000754[2:2] = 0x00000000U // .. ==> MASK : 0x00000004U VAL : 0x00000000U // .. L2_SEL = 0 // .. ==> 0XF8000754[4:3] = 0x00000000U // .. ==> MASK : 0x00000018U VAL : 0x00000000U // .. L3_SEL = 4 // .. ==> 0XF8000754[7:5] = 0x00000004U // .. ==> MASK : 0x000000E0U VAL : 0x00000080U // .. Speed = 0 // .. ==> 0XF8000754[8:8] = 0x00000000U // .. ==> MASK : 0x00000100U VAL : 0x00000000U // .. IO_Type = 1 // .. ==> 0XF8000754[11:9] = 0x00000001U // .. ==> MASK : 0x00000E00U VAL : 0x00000200U // .. PULLUP = 1 // .. ==> 0XF8000754[12:12] = 0x00000001U // .. ==> MASK : 0x00001000U VAL : 0x00001000U // .. DisableRcvr = 0 // .. ==> 0XF8000754[13:13] = 0x00000000U // .. ==> MASK : 0x00002000U VAL : 0x00000000U // .. EMIT_MASKWRITE(0XF8000754, 0x00003FFFU ,0x00001280U), // .. SDIO0_WP_SEL = 55 // .. ==> 0XF8000830[5:0] = 0x00000037U // .. ==> MASK : 0x0000003FU VAL : 0x00000037U // .. SDIO0_CD_SEL = 56 // .. ==> 0XF8000830[21:16] = 0x00000038U // .. ==> MASK : 0x003F0000U VAL : 0x00380000U // .. EMIT_MASKWRITE(0XF8000830, 0x003F003FU ,0x00380037U), // .. FINISH: MIO PROGRAMMING // .. START: LOCK IT BACK // .. LOCK_KEY = 0X767B // .. ==> 0XF8000004[15:0] = 0x0000767BU // .. ==> MASK : 0x0000FFFFU VAL : 0x0000767BU // .. EMIT_WRITE(0XF8000004, 0x0000767BU), // .. FINISH: LOCK IT BACK // FINISH: top // EMIT_EXIT(), // }; unsigned long ps7_peripherals_init_data_1_0[] = { // START: top // .. START: SLCR SETTINGS // .. UNLOCK_KEY = 0XDF0D // .. ==> 0XF8000008[15:0] = 0x0000DF0DU // .. ==> MASK : 0x0000FFFFU VAL : 0x0000DF0DU // .. EMIT_WRITE(0XF8000008, 0x0000DF0DU), // .. FINISH: SLCR SETTINGS // .. START: LOCK IT BACK // .. LOCK_KEY = 0X767B // .. ==> 0XF8000004[15:0] = 0x0000767BU // .. ==> MASK : 0x0000FFFFU VAL : 0x0000767BU // .. EMIT_WRITE(0XF8000004, 0x0000767BU), // .. FINISH: LOCK IT BACK // .. START: SRAM/NOR SET OPMODE // .. FINISH: SRAM/NOR SET OPMODE // .. START: UART REGISTERS // .. FINISH: UART REGISTERS // .. START: QSPI REGISTERS // .. Holdb_dr = 1 // .. ==> 0XE000D000[19:19] = 0x00000001U // .. ==> MASK : 0x00080000U VAL : 0x00080000U // .. EMIT_MASKWRITE(0XE000D000, 0x00080000U ,0x00080000U), // .. FINISH: QSPI REGISTERS // .. START: PL POWER ON RESET REGISTERS // .. PCFG_POR_CNT_4K = 0 // .. ==> 0XF8007000[29:29] = 0x00000000U // .. ==> MASK : 0x20000000U VAL : 0x00000000U // .. EMIT_MASKWRITE(0XF8007000, 0x20000000U ,0x00000000U), // .. FINISH: PL POWER ON RESET REGISTERS // .. START: SMC TIMING CALCULATION REGISTER UPDATE // .. .. START: NAND SET CYCLE // .. .. FINISH: NAND SET CYCLE // .. .. START: OPMODE // .. .. FINISH: OPMODE // .. .. START: DIRECT COMMAND // .. .. FINISH: DIRECT COMMAND // .. .. START: SRAM/NOR CS0 SET CYCLE // .. .. FINISH: SRAM/NOR CS0 SET CYCLE // .. .. START: DIRECT COMMAND // .. .. FINISH: DIRECT COMMAND // .. .. START: NOR CS0 BASE ADDRESS // .. .. FINISH: NOR CS0 BASE ADDRESS // .. .. START: SRAM/NOR CS1 SET CYCLE // .. .. FINISH: SRAM/NOR CS1 SET CYCLE // .. .. START: DIRECT COMMAND // .. .. FINISH: DIRECT COMMAND // .. .. START: NOR CS1 BASE ADDRESS // .. .. FINISH: NOR CS1 BASE ADDRESS // .. .. START: USB RESET // .. .. FINISH: USB RESET // .. .. START: ENET RESET // .. .. FINISH: ENET RESET // .. .. START: I2C RESET // .. .. FINISH: I2C RESET // .. .. START: NOR CHIP SELECT // .. .. .. START: DIR MODE BANK 0 // .. .. .. FINISH: DIR MODE BANK 0 // .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] // .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] // .. .. .. START: OUTPUT ENABLE BANK 0 // .. .. .. FINISH: OUTPUT ENABLE BANK 0 // .. .. FINISH: NOR CHIP SELECT // .. FINISH: SMC TIMING CALCULATION REGISTER UPDATE // FINISH: top // EMIT_EXIT(), // }; unsigned long ps7_post_config_1_0[] = { // START: top // .. START: SLCR SETTINGS // .. UNLOCK_KEY = 0XDF0D // .. ==> 0XF8000008[15:0] = 0x0000DF0DU // .. ==> MASK : 0x0000FFFFU VAL : 0x0000DF0DU // .. EMIT_WRITE(0XF8000008, 0x0000DF0DU), // .. FINISH: SLCR SETTINGS // .. START: ENABLING LEVEL SHIFTER // .. USER_INP_ICT_EN_0 = 3 // .. ==> 0XF8000900[1:0] = 0x00000003U // .. ==> MASK : 0x00000003U VAL : 0x00000003U // .. USER_INP_ICT_EN_1 = 3 // .. ==> 0XF8000900[3:2] = 0x00000003U // .. ==> MASK : 0x0000000CU VAL : 0x0000000CU // .. EMIT_MASKWRITE(0XF8000900, 0x0000000FU ,0x0000000FU), // .. FINISH: ENABLING LEVEL SHIFTER // .. START: FPGA RESETS TO 0 // .. reserved_3 = 0 // .. ==> 0XF8000240[31:25] = 0x00000000U // .. ==> MASK : 0xFE000000U VAL : 0x00000000U // .. FPGA_ACP_RST = 0 // .. ==> 0XF8000240[24:24] = 0x00000000U // .. ==> MASK : 0x01000000U VAL : 0x00000000U // .. FPGA_AXDS3_RST = 0 // .. ==> 0XF8000240[23:23] = 0x00000000U // .. ==> MASK : 0x00800000U VAL : 0x00000000U // .. FPGA_AXDS2_RST = 0 // .. ==> 0XF8000240[22:22] = 0x00000000U // .. ==> MASK : 0x00400000U VAL : 0x00000000U // .. FPGA_AXDS1_RST = 0 // .. ==> 0XF8000240[21:21] = 0x00000000U // .. ==> MASK : 0x00200000U VAL : 0x00000000U // .. FPGA_AXDS0_RST = 0 // .. ==> 0XF8000240[20:20] = 0x00000000U // .. ==> MASK : 0x00100000U VAL : 0x00000000U // .. reserved_2 = 0 // .. ==> 0XF8000240[19:18] = 0x00000000U // .. ==> MASK : 0x000C0000U VAL : 0x00000000U // .. FSSW1_FPGA_RST = 0 // .. ==> 0XF8000240[17:17] = 0x00000000U // .. ==> MASK : 0x00020000U VAL : 0x00000000U // .. FSSW0_FPGA_RST = 0 // .. ==> 0XF8000240[16:16] = 0x00000000U // .. ==> MASK : 0x00010000U VAL : 0x00000000U // .. reserved_1 = 0 // .. ==> 0XF8000240[15:14] = 0x00000000U // .. ==> MASK : 0x0000C000U VAL : 0x00000000U // .. FPGA_FMSW1_RST = 0 // .. ==> 0XF8000240[13:13] = 0x00000000U // .. ==> MASK : 0x00002000U VAL : 0x00000000U // .. FPGA_FMSW0_RST = 0 // .. ==> 0XF8000240[12:12] = 0x00000000U // .. ==> MASK : 0x00001000U VAL : 0x00000000U // .. FPGA_DMA3_RST = 0 // .. ==> 0XF8000240[11:11] = 0x00000000U // .. ==> MASK : 0x00000800U VAL : 0x00000000U // .. FPGA_DMA2_RST = 0 // .. ==> 0XF8000240[10:10] = 0x00000000U // .. ==> MASK : 0x00000400U VAL : 0x00000000U // .. FPGA_DMA1_RST = 0 // .. ==> 0XF8000240[9:9] = 0x00000000U // .. ==> MASK : 0x00000200U VAL : 0x00000000U // .. FPGA_DMA0_RST = 0 // .. ==> 0XF8000240[8:8] = 0x00000000U // .. ==> MASK : 0x00000100U VAL : 0x00000000U // .. reserved = 0 // .. ==> 0XF8000240[7:4] = 0x00000000U // .. ==> MASK : 0x000000F0U VAL : 0x00000000U // .. FPGA3_OUT_RST = 0 // .. ==> 0XF8000240[3:3] = 0x00000000U // .. ==> MASK : 0x00000008U VAL : 0x00000000U // .. FPGA2_OUT_RST = 0 // .. ==> 0XF8000240[2:2] = 0x00000000U // .. ==> MASK : 0x00000004U VAL : 0x00000000U // .. FPGA1_OUT_RST = 0 // .. ==> 0XF8000240[1:1] = 0x00000000U // .. ==> MASK : 0x00000002U VAL : 0x00000000U // .. FPGA0_OUT_RST = 0 // .. ==> 0XF8000240[0:0] = 0x00000000U // .. ==> MASK : 0x00000001U VAL : 0x00000000U // .. EMIT_MASKWRITE(0XF8000240, 0xFFFFFFFFU ,0x00000000U), // .. FINISH: FPGA RESETS TO 0 // .. START: AFI REGISTERS // .. .. START: AFI0 REGISTERS // .. .. FINISH: AFI0 REGISTERS // .. .. START: AFI1 REGISTERS // .. .. FINISH: AFI1 REGISTERS // .. .. START: AFI2 REGISTERS // .. .. FINISH: AFI2 REGISTERS // .. .. START: AFI3 REGISTERS // .. .. FINISH: AFI3 REGISTERS // .. FINISH: AFI REGISTERS // .. START: LOCK IT BACK // .. LOCK_KEY = 0X767B // .. ==> 0XF8000004[15:0] = 0x0000767BU // .. ==> MASK : 0x0000FFFFU VAL : 0x0000767BU // .. EMIT_WRITE(0XF8000004, 0x0000767BU), // .. FINISH: LOCK IT BACK // FINISH: top // EMIT_EXIT(), // }; unsigned long ps7_debug_1_0[] = { // START: top // .. START: CROSS TRIGGER CONFIGURATIONS // .. .. START: UNLOCKING CTI REGISTERS // .. .. KEY = 0XC5ACCE55 // .. .. ==> 0XF8898FB0[31:0] = 0xC5ACCE55U // .. .. ==> MASK : 0xFFFFFFFFU VAL : 0xC5ACCE55U // .. .. EMIT_WRITE(0XF8898FB0, 0xC5ACCE55U), // .. .. KEY = 0XC5ACCE55 // .. .. ==> 0XF8899FB0[31:0] = 0xC5ACCE55U // .. .. ==> MASK : 0xFFFFFFFFU VAL : 0xC5ACCE55U // .. .. EMIT_WRITE(0XF8899FB0, 0xC5ACCE55U), // .. .. KEY = 0XC5ACCE55 // .. .. ==> 0XF8809FB0[31:0] = 0xC5ACCE55U // .. .. ==> MASK : 0xFFFFFFFFU VAL : 0xC5ACCE55U // .. .. EMIT_WRITE(0XF8809FB0, 0xC5ACCE55U), // .. .. FINISH: UNLOCKING CTI REGISTERS // .. .. START: ENABLING CTI MODULES AND CHANNELS // .. .. FINISH: ENABLING CTI MODULES AND CHANNELS // .. .. START: MAPPING CPU0, CPU1 AND FTM EVENTS TO CTM CHANNELS // .. .. FINISH: MAPPING CPU0, CPU1 AND FTM EVENTS TO CTM CHANNELS // .. FINISH: CROSS TRIGGER CONFIGURATIONS // FINISH: top // EMIT_EXIT(), // }; unsigned long ps7_ddr_init_data_1_0[] = {}; unsigned long ps7_ddr_init_data_2_0[] = {}; unsigned long ps7_ddr_init_data_3_0[] = {}; #include "xil_io.h" #define PS7_MASK_POLL_TIME 100000000 char* getPS7MessageInfo(unsigned key) { char* err_msg = ""; switch (key) { case PS7_INIT_SUCCESS: err_msg = "PS7 initialization successful"; break; case PS7_INIT_CORRUPT: err_msg = "PS7 init Data Corrupted"; break; case PS7_INIT_TIMEOUT: err_msg = "PS7 init mask poll timeout"; break; case PS7_POLL_FAILED_DDR_INIT: err_msg = "Mask Poll failed for DDR Init"; break; case PS7_POLL_FAILED_DMA: err_msg = "Mask Poll failed for PLL Init"; break; case PS7_POLL_FAILED_PLL: err_msg = "Mask Poll failed for DMA done bit"; break; default: err_msg = "Undefined error status"; break; } return err_msg; } unsigned long ps7GetSiliconVersion () { // Read PS version from MCTRL register [31:28] unsigned long mask = 0xF0000000; unsigned long *addr = (unsigned long*) 0XF8007080; unsigned long ps_version = (*addr & mask) >> 28; return ps_version; } void mask_write (unsigned long add , unsigned long mask, unsigned long val ) { volatile unsigned long *addr = (volatile unsigned long*) add; *addr = ( val & mask ) | ( *addr & ~mask); //xil_printf("MaskWrite : 0x%x--> 0x%x \n \r" ,add, *addr); } int mask_poll(unsigned long add , unsigned long mask ) { volatile unsigned long *addr = (volatile unsigned long*) add; int i = 0; while (!(*addr & mask)) { if (i == PS7_MASK_POLL_TIME) { return -1; } i++; } return 1; //xil_printf("MaskPoll : 0x%x --> 0x%x \n \r" , add, *addr); } unsigned long mask_read(unsigned long add , unsigned long mask ) { volatile unsigned long *addr = (volatile unsigned long*) add; unsigned long val = (*addr & mask); //xil_printf("MaskRead : 0x%x --> 0x%x \n \r" , add, val); return val; } int ps7_config(unsigned long * ps7_config_init) { unsigned long *ptr = ps7_config_init; unsigned long opcode; // current instruction .. unsigned long args[16]; // no opcode has so many args ... int numargs; // number of arguments of this instruction int j; // general purpose index volatile unsigned long *addr; // some variable to make code readable unsigned long val,mask; // some variable to make code readable int finish = -1 ; // loop while this is negative ! int i = 0; // Timeout variable while( finish < 0 ) { numargs = ptr[0] & 0xF; opcode = ptr[0] >> 4; for( j = 0 ; j < numargs ; j ++ ) args[j] = ptr[j+1]; ptr += numargs + 1; switch ( opcode ) { case OPCODE_EXIT: finish = PS7_INIT_SUCCESS; break; case OPCODE_CLEAR: addr = (unsigned long*) args[0]; *addr = 0; break; case OPCODE_WRITE: addr = (unsigned long*) args[0]; val = args[1]; *addr = val; break; case OPCODE_MASKWRITE: addr = (unsigned long*) args[0]; mask = args[1]; val = args[2]; *addr = ( val & mask ) | ( *addr & ~mask); break; case OPCODE_MASKPOLL: addr = (unsigned long*) args[0]; mask = args[1]; i = 0; while (!(*addr & mask)) { if (i == PS7_MASK_POLL_TIME) { finish = PS7_INIT_TIMEOUT; break; } i++; } break; case OPCODE_MASKDELAY: { addr = (unsigned long*) args[0]; mask = args[1]; int delay = get_number_of_cycles_for_delay(mask); perf_reset_and_start_timer(); while ((*addr < delay)) { } } break; default: finish = PS7_INIT_CORRUPT; break; } } return finish; } unsigned long *ps7_mio_init_data = ps7_mio_init_data_3_0; unsigned long *ps7_pll_init_data = ps7_pll_init_data_3_0; unsigned long *ps7_clock_init_data = ps7_clock_init_data_3_0; unsigned long *ps7_ddr_init_data = ps7_ddr_init_data_3_0; unsigned long *ps7_peripherals_init_data = ps7_peripherals_init_data_3_0; int ps7_post_config() { // Get the PS_VERSION on run time unsigned long si_ver = ps7GetSiliconVersion (); int ret = -1; if (si_ver == PCW_SILICON_VERSION_1) { ret = ps7_config (ps7_post_config_1_0); if (ret != PS7_INIT_SUCCESS) return ret; } else if (si_ver == PCW_SILICON_VERSION_2) { ret = ps7_config (ps7_post_config_2_0); if (ret != PS7_INIT_SUCCESS) return ret; } else { ret = ps7_config (ps7_post_config_3_0); if (ret != PS7_INIT_SUCCESS) return ret; } return PS7_INIT_SUCCESS; } int ps7_debug() { // Get the PS_VERSION on run time unsigned long si_ver = ps7GetSiliconVersion (); int ret = -1; if (si_ver == PCW_SILICON_VERSION_1) { ret = ps7_config (ps7_debug_1_0); if (ret != PS7_INIT_SUCCESS) return ret; } else if (si_ver == PCW_SILICON_VERSION_2) { ret = ps7_config (ps7_debug_2_0); if (ret != PS7_INIT_SUCCESS) return ret; } else { ret = ps7_config (ps7_debug_3_0); if (ret != PS7_INIT_SUCCESS) return ret; } return PS7_INIT_SUCCESS; } int ps7_init() { // Get the PS_VERSION on run time unsigned long si_ver = ps7GetSiliconVersion (); int ret; //int pcw_ver = 0; if (si_ver == PCW_SILICON_VERSION_1) { ps7_mio_init_data = ps7_mio_init_data_1_0; ps7_pll_init_data = ps7_pll_init_data_1_0; ps7_clock_init_data = ps7_clock_init_data_1_0; ps7_ddr_init_data = ps7_ddr_init_data_1_0; ps7_peripherals_init_data = ps7_peripherals_init_data_1_0; //pcw_ver = 1; } else if (si_ver == PCW_SILICON_VERSION_2) { ps7_mio_init_data = ps7_mio_init_data_2_0; ps7_pll_init_data = ps7_pll_init_data_2_0; ps7_clock_init_data = ps7_clock_init_data_2_0; ps7_ddr_init_data = ps7_ddr_init_data_2_0; ps7_peripherals_init_data = ps7_peripherals_init_data_2_0; //pcw_ver = 2; } else { ps7_mio_init_data = ps7_mio_init_data_3_0; ps7_pll_init_data = ps7_pll_init_data_3_0; ps7_clock_init_data = ps7_clock_init_data_3_0; ps7_ddr_init_data = ps7_ddr_init_data_3_0; ps7_peripherals_init_data = ps7_peripherals_init_data_3_0; //pcw_ver = 3; } // MIO init ret = ps7_config (ps7_mio_init_data); if (ret != PS7_INIT_SUCCESS) return ret; // PLL init ret = ps7_config (ps7_pll_init_data); if (ret != PS7_INIT_SUCCESS) return ret; // Clock init ret = ps7_config (ps7_clock_init_data); if (ret != PS7_INIT_SUCCESS) return ret; // DDR init ret = ps7_config (ps7_ddr_init_data); if (ret != PS7_INIT_SUCCESS) return ret; // Peripherals init ret = ps7_config (ps7_peripherals_init_data); if (ret != PS7_INIT_SUCCESS) return ret; //xil_printf ("\n PCW Silicon Version : %d.0", pcw_ver); return PS7_INIT_SUCCESS; } /* For delay calculation using global timer */ /* start timer */ void perf_start_clock(void) { *(volatile unsigned int*)SCU_GLOBAL_TIMER_CONTROL = ((1 << 0) | // Timer Enable (1 << 3) | // Auto-increment (0 << 8) // Pre-scale ); } /* stop timer and reset timer count regs */ void perf_reset_clock(void) { perf_disable_clock(); *(volatile unsigned int*)SCU_GLOBAL_TIMER_COUNT_L32 = 0; *(volatile unsigned int*)SCU_GLOBAL_TIMER_COUNT_U32 = 0; } /* Compute mask for given delay in miliseconds*/ int get_number_of_cycles_for_delay(unsigned int delay) { // GTC is always clocked at 1/2 of the CPU frequency (CPU_3x2x) return (APU_FREQ*delay/(2*1000)); } /* stop timer */ void perf_disable_clock(void) { *(volatile unsigned int*)SCU_GLOBAL_TIMER_CONTROL = 0; } void perf_reset_and_start_timer() { perf_reset_clock(); perf_start_clock(); }