xilinx.com BlockDiagram system 1.00.a isTop true DDR TIMEPERIOD_PS 1250 MEMORY_TYPE COMPONENTS DATA_WIDTH 8 CS_ENABLED true DATA_MASK_ENABLED true SLOT Single MEM_ADDR_MAP ROW_COLUMN_BANK BURST_LENGTH 8 AXI_ARBITRATION_SCHEME TDM CAS_LATENCY 11 CAS_WRITE_LATENCY 11 FIXED_IO M_AXI_GP0 DATA_WIDTH 32 PROTOCOL AXI3 FREQ_HZ 125000000 ID_WIDTH 12 ADDR_WIDTH 32 AWUSER_WIDTH 0 ARUSER_WIDTH 0 WUSER_WIDTH 0 RUSER_WIDTH 0 BUSER_WIDTH 0 READ_WRITE_MODE READ_WRITE HAS_BURST 1 HAS_LOCK 1 HAS_PROT 1 HAS_CACHE 1 HAS_QOS 1 HAS_REGION 0 HAS_WSTRB 1 HAS_BRESP 1 HAS_RRESP 1 SUPPORTS_NARROW_BURST 0 NUM_READ_OUTSTANDING 8 NUM_WRITE_OUTSTANDING 8 MAX_BURST_LENGTH 16 PHASE 0.000 CLK_DOMAIN system_M_AXI_GP0_ACLK S_AXI_HP0 DATA_WIDTH 64 PROTOCOL AXI3 FREQ_HZ 125000000 ID_WIDTH 0 ADDR_WIDTH 32 AWUSER_WIDTH 0 ARUSER_WIDTH 0 WUSER_WIDTH 0 RUSER_WIDTH 0 BUSER_WIDTH 0 READ_WRITE_MODE READ_WRITE HAS_BURST 1 HAS_LOCK 1 HAS_PROT 1 HAS_CACHE 1 HAS_QOS 1 HAS_REGION 1 HAS_WSTRB 1 HAS_BRESP 1 HAS_RRESP 1 SUPPORTS_NARROW_BURST 1 NUM_READ_OUTSTANDING 1 NUM_WRITE_OUTSTANDING 1 MAX_BURST_LENGTH 16 PHASE 0.000 CLK_DOMAIN system_S_AXI_HP0_aclk S_AXI_HP1 DATA_WIDTH 64 PROTOCOL AXI3 FREQ_HZ 125000000 ID_WIDTH 0 ADDR_WIDTH 32 AWUSER_WIDTH 0 ARUSER_WIDTH 0 WUSER_WIDTH 0 RUSER_WIDTH 0 BUSER_WIDTH 0 READ_WRITE_MODE READ_WRITE HAS_BURST 1 HAS_LOCK 1 HAS_PROT 1 HAS_CACHE 1 HAS_QOS 1 HAS_REGION 1 HAS_WSTRB 1 HAS_BRESP 1 HAS_RRESP 1 SUPPORTS_NARROW_BURST 1 NUM_READ_OUTSTANDING 1 NUM_WRITE_OUTSTANDING 1 MAX_BURST_LENGTH 16 PHASE 0.000 CLK_DOMAIN system_S_AXI_HP1_aclk Vaux0 Vaux1 Vaux8 Vaux9 Vp_Vn CLK.FCLK_CLK0 Clk Clock CLK FCLK_CLK0 FREQ_HZ 125000000 PHASE 0.000 CLK_DOMAIN system_processing_system7_0_FCLK_CLK0 CLK.FCLK_CLK1 Clk Clock CLK FCLK_CLK1 FREQ_HZ 250000000 PHASE 0.000 CLK_DOMAIN system_processing_system7_0_FCLK_CLK1 CLK.FCLK_CLK2 Clk Clock CLK FCLK_CLK2 FREQ_HZ 50000000 PHASE 0.000 CLK_DOMAIN system_processing_system7_0_FCLK_CLK2 CLK.FCLK_CLK3 Clk Clock CLK FCLK_CLK3 FREQ_HZ 200000000 PHASE 0.000 CLK_DOMAIN system_processing_system7_0_FCLK_CLK3 RST.FCLK_RESET0_N Reset Reset RST FCLK_RESET0_N POLARITY ACTIVE_LOW RST.FCLK_RESET1_N Reset Reset RST FCLK_RESET1_N POLARITY ACTIVE_LOW RST.FCLK_RESET2_N Reset Reset RST FCLK_RESET2_N POLARITY ACTIVE_LOW RST.FCLK_RESET3_N Reset Reset RST FCLK_RESET3_N POLARITY ACTIVE_LOW CLK.M_AXI_GP0_ACLK Clk Clock CLK M_AXI_GP0_ACLK FREQ_HZ 125000000 PHASE 0.000 CLK_DOMAIN system_M_AXI_GP0_ACLK ASSOCIATED_BUSIF M_AXI_GP0 CLK.S_AXI_HP0_ACLK Clk Clock CLK S_AXI_HP0_aclk FREQ_HZ 125000000 PHASE 0.000 CLK_DOMAIN system_S_AXI_HP0_aclk ASSOCIATED_BUSIF S_AXI_HP0 CLK.S_AXI_HP1_ACLK Clk Clock CLK S_AXI_HP1_aclk FREQ_HZ 125000000 PHASE 0.000 CLK_DOMAIN system_S_AXI_HP1_aclk ASSOCIATED_BUSIF S_AXI_HP1 BlockDiagram :vivado.xilinx.com: FCLK_CLK0 out FCLK_CLK1 out FCLK_CLK2 out FCLK_CLK3 out FCLK_RESET0_N out FCLK_RESET1_N out FCLK_RESET2_N out FCLK_RESET3_N out M_AXI_GP0_ACLK in S_AXI_HP0_aclk in S_AXI_HP1_aclk in S_AXI_HP0 4G 32 SEG_processing_system7_0_HP0_DDR_LOWOCM /processing_system7/S_AXI_HP0/HP0_DDR_LOWOCM 0x00000000 512M S_AXI_HP1 4G 32 SEG_processing_system7_0_HP1_DDR_LOWOCM /processing_system7/S_AXI_HP1/HP1_DDR_LOWOCM 0x00000000 512M M_AXI_GP0 Reg 0 64K 32 register xilinx.com BlockDiagram system_imp 1.00.a axi_protocol_converter_0 system_axi_protocol_converter_0_0 proc_sys_reset system_proc_sys_reset_0 1 processing_system7 system_processing_system7_0 125 125 250 200 1 1 1 1 1 1 1 1 1 1 1 LVCMOS 2.5V 16 Bit MT41J256M16 RE-125 1 1 MIO 16 .. 27 1 1 1 MIO 46 1 MIO 47 1 MIO 14 .. 15 1 MIO 8 .. 9 0 1 MIO 10 .. 15 1 1 1 MIO 48 1 MIO 50 .. 51 1 ARM PLL ARM PLL disabled fast disabled fast disabled fast disabled fast disabled fast disabled fast disabled fast disabled fast disabled fast disabled fast disabled fast disabled fast disabled fast disabled fast disabled fast disabled fast disabled fast disabled fast disabled fast disabled fast disabled fast disabled fast disabled fast disabled fast xadc system_xadc_0 independent_adc Off TEMPERATURE VP_VN true true true true true false xlconstant system_xlconstant_0 axi_protocol_converter_0_M_AXI processing_system7_0_M_AXI_GP1 m_axi_gp0_aclk_1 proc_sys_reset_0_interconnect_aresetn proc_sys_reset_0_peripheral_aresetn processing_system7_0_fclk_clk0 processing_system7_0_fclk_clk1 processing_system7_0_fclk_clk2 processing_system7_0_fclk_clk3 processing_system7_0_fclk_reset0_n processing_system7_0_fclk_reset1_n processing_system7_0_fclk_reset2_n processing_system7_0_fclk_reset3_n s_axi_hp0_aclk s_axi_hp1_aclk xadc_wiz_0_ip2intc_irpt xlconstant_dout xilinx.com Addressing/processing_system7 processing_system7 5.5 Data 4G 32 SEG_system_Reg /M_AXI_GP0/Reg 0x40000000 1G SEG_xadc_wiz_0_Reg /xadc/s_axi_lite/Reg 0x83C00000 64K