Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved.
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| Tool Version     : Vivado v.2024.2 (win64) Build 5239630 Fri Nov 08 22:35:27 MST 2024
| Date             : Mon Feb  2 21:05:32 2026
| Host             : PCLDY-ESGT-419 running 64-bit major release  (build 9200)
| Command          : report_power -file out/post_synth_power.rpt
| Design           : red_pitaya_top
| Device           : xc7z010clg400-1
| Design State     : synthesized
| Grade            : commercial
| Process          : typical
| Characterization : Production
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Power Report

Table of Contents
-----------------
1. Summary
1.1 On-Chip Components
1.2 Power Supply Summary
1.3 Confidence Level
2. Settings
2.1 Environment
2.2 Clock Constraints
3. Detailed Reports
3.1 By Hierarchy

1. Summary
----------

+--------------------------+--------------+
| Total On-Chip Power (W)  | 2.246        |
| Design Power Budget (W)  | Unspecified* |
| Power Budget Margin (W)  | NA           |
| Dynamic (W)              | 2.104        |
| Device Static (W)        | 0.142        |
| Effective TJA (C/W)      | 11.5         |
| Max Ambient (C)          | 59.1         |
| Junction Temperature (C) | 50.9         |
| Confidence Level         | Low          |
| Setting File             | ---          |
| Simulation Activity File | ---          |
| Design Nets Matched      | NA           |
+--------------------------+--------------+
* Specify Design Power Budget using, set_operating_conditions -design_power_budget <value in Watts>


1.1 On-Chip Components
----------------------

+-------------------------+-----------+----------+-----------+-----------------+
| On-Chip                 | Power (W) | Used     | Available | Utilization (%) |
+-------------------------+-----------+----------+-----------+-----------------+
| Clocks                  |     0.071 |       15 |       --- |             --- |
| Slice Logic             |     0.125 |    34609 |       --- |             --- |
|   LUT as Logic          |     0.104 |    16145 |     17600 |           91.73 |
|   CARRY4                |     0.016 |     1458 |      4400 |           33.14 |
|   Register              |     0.005 |    13948 |     35200 |           39.63 |
|   F7/F8 Muxes           |    <0.001 |      556 |     17600 |            3.16 |
|   LUT as Shift Register |    <0.001 |       51 |      6000 |            0.85 |
|   Others                |     0.000 |      435 |       --- |             --- |
|   BUFG                  |     0.000 |        1 |        32 |            3.13 |
| Signals                 |     0.125 |    29790 |       --- |             --- |
| Block RAM               |     0.103 |       34 |        60 |           56.67 |
| PLL                     |     0.097 |        1 |         2 |           50.00 |
| DSPs                    |     0.042 |       46 |        80 |           57.50 |
| I/O                     |     0.244 |       91 |       100 |           91.00 |
| XADC                    |     0.004 |        1 |       --- |             --- |
| PS7                     |     1.292 |        1 |       --- |             --- |
| Static Power            |     0.142 |          |           |                 |
| Total                   |     2.245 |          |           |                 |
+-------------------------+-----------+----------+-----------+-----------------+


1.2 Power Supply Summary
------------------------

+-----------+-------------+-----------+-------------+------------+-------------+-------------+------------+
| Source    | Voltage (V) | Total (A) | Dynamic (A) | Static (A) | Powerup (A) | Budget (A)  | Margin (A) |
+-----------+-------------+-----------+-------------+------------+-------------+-------------+------------+
| Vccint    |       1.000 |     0.478 |       0.468 |      0.010 |       NA    | Unspecified | NA         |
| Vccaux    |       1.800 |     0.065 |       0.056 |      0.009 |       NA    | Unspecified | NA         |
| Vcco33    |       3.300 |     0.071 |       0.070 |      0.001 |       NA    | Unspecified | NA         |
| Vcco25    |       2.500 |     0.000 |       0.000 |      0.000 |       NA    | Unspecified | NA         |
| Vcco18    |       1.800 |     0.002 |       0.001 |      0.001 |       NA    | Unspecified | NA         |
| Vcco15    |       1.500 |     0.000 |       0.000 |      0.000 |       NA    | Unspecified | NA         |
| Vcco135   |       1.350 |     0.000 |       0.000 |      0.000 |       NA    | Unspecified | NA         |
| Vcco12    |       1.200 |     0.000 |       0.000 |      0.000 |       NA    | Unspecified | NA         |
| Vccaux_io |       1.800 |     0.000 |       0.000 |      0.000 |       NA    | Unspecified | NA         |
| Vccbram   |       1.000 |     0.012 |       0.008 |      0.003 |       NA    | Unspecified | NA         |
| MGTAVcc   |       1.000 |     0.000 |       0.000 |      0.000 |       NA    | Unspecified | NA         |
| MGTAVtt   |       1.200 |     0.000 |       0.000 |      0.000 |       NA    | Unspecified | NA         |
| MGTVccaux |       1.800 |     0.000 |       0.000 |      0.000 |       NA    | Unspecified | NA         |
| Vccpint   |       1.000 |     0.715 |       0.678 |      0.037 |       NA    | Unspecified | NA         |
| Vccpaux   |       1.800 |     0.038 |       0.027 |      0.010 |       NA    | Unspecified | NA         |
| Vccpll    |       1.800 |     0.017 |       0.014 |      0.003 |       NA    | Unspecified | NA         |
| Vcco_ddr  |       1.500 |     0.356 |       0.354 |      0.002 |       NA    | Unspecified | NA         |
| Vcco_mio0 |       3.300 |     0.002 |       0.001 |      0.001 |       NA    | Unspecified | NA         |
| Vcco_mio1 |       2.500 |     0.003 |       0.002 |      0.001 |       NA    | Unspecified | NA         |
| Vccadc    |       1.800 |     0.022 |       0.002 |      0.020 |       NA    | Unspecified | NA         |
+-----------+-------------+-----------+-------------+------------+-------------+-------------+------------+


1.3 Confidence Level
--------------------

+-----------------------------+------------+--------------------------------------------------------+------------------------------------------------------------------------------------------------------------+
| User Input Data             | Confidence | Details                                                | Action                                                                                                     |
+-----------------------------+------------+--------------------------------------------------------+------------------------------------------------------------------------------------------------------------+
| Design implementation state | Low        | Design is synthesized                                  | Accuracy of the tool is not optimal until design is fully placed and routed                                |
| Clock nodes activity        | High       | User specified more than 95% of clocks                 |                                                                                                            |
| I/O nodes activity          | Low        | More than 75% of inputs are missing user specification | Provide missing input activity with simulation results or by editing the "By Resource Type -> I/Os" view   |
| Internal nodes activity     | Medium     | User specified less than 25% of internal nodes         | Provide missing internal nodes activity with simulation results or by editing the "By Resource Type" views |
| Device models               | High       | Device models are Production                           |                                                                                                            |
|                             |            |                                                        |                                                                                                            |
| Overall confidence level    | Low        |                                                        |                                                                                                            |
+-----------------------------+------------+--------------------------------------------------------+------------------------------------------------------------------------------------------------------------+


2. Settings
-----------

2.1 Environment
---------------

+-----------------------+------------------------+
| Ambient Temp (C)      | 25.0                   |
| ThetaJA (C/W)         | 11.5                   |
| Airflow (LFM)         | 250                    |
| Heat Sink             | none                   |
| ThetaSA (C/W)         | 0.0                    |
| Board Selection       | medium (10"x10")       |
| # of Board Layers     | 8to11 (8 to 11 Layers) |
| Board Temperature (C) | 25.0                   |
+-----------------------+------------------------+


2.2 Clock Constraints
---------------------

+----------------+-----------------------------------------------------------------------+-----------------+
| Clock          | Domain                                                                | Constraint (ns) |
+----------------+-----------------------------------------------------------------------+-----------------+
| adc_clk        | adc_clk_p_i                                                           |             8.0 |
| clk_fb         | pll/clk_fb                                                            |             8.0 |
| clk_fpga_0     | i_ps/system_i/system_i/processing_system7/inst/FCLK_CLK_unbuffered[0] |             8.0 |
| clk_fpga_1     | i_ps/system_i/system_i/processing_system7/inst/FCLK_CLK_unbuffered[1] |             4.0 |
| clk_fpga_2     | i_ps/system_i/system_i/processing_system7/inst/FCLK_CLK_unbuffered[2] |            20.0 |
| clk_fpga_3     | i_ps/system_i/system_i/processing_system7/inst/FCLK_CLK_unbuffered[3] |             5.0 |
| pll_adc_clk    | pll/clk_adc                                                           |             8.0 |
| pll_dac_clk_1x | pll/clk_dac_1x                                                        |             8.0 |
| pll_dac_clk_2p | pll/clk_dac_2p                                                        |             4.0 |
| pll_dac_clk_2x | pll/clk_dac_2x                                                        |             4.0 |
| pll_pwm_clk    | pll/clk_pwm                                                           |             4.0 |
| pll_ser_clk    | pll/clk_ser                                                           |             4.0 |
+----------------+-----------------------------------------------------------------------+-----------------+


3. Detailed Reports
-------------------

3.1 By Hierarchy
----------------

+-----------------------------+-----------+
| Name                        | Power (W) |
+-----------------------------+-----------+
| red_pitaya_top              |     2.104 |
|   i_ams                     |     0.001 |
|   i_asg                     |     0.060 |
|     adv_trig_a              |     0.001 |
|     adv_trig_b              |     0.001 |
|     ch[0]                   |     0.025 |
|     ch[1]                   |     0.025 |
|     prng                    |     0.002 |
|   i_dsp                     |     0.313 |
|     genblk2[0].i_pid        |     0.022 |
|       pidfilter             |     0.011 |
|     genblk2[1].i_pid        |     0.022 |
|       pidfilter             |     0.011 |
|     genblk2[2].i_pid        |     0.022 |
|       pidfilter             |     0.011 |
|     genblk3[3].i_trigger    |     0.006 |
|       triggerfilter         |     0.003 |
|     genblk4[4].iir          |     0.031 |
|       iir_inputfilter       |     0.002 |
|       p_ay1_module          |     0.003 |
|       p_bx1_module          |     0.003 |
|     genblk5[5].iq           |     0.058 |
|       demodulator           |     0.004 |
|       inputfilter           |     0.003 |
|       iq_fgen               |     0.018 |
|       iqfilter[0]           |     0.008 |
|       iqfilter[1]           |     0.008 |
|       modulator             |     0.010 |
|     genblk5[6].iq           |     0.058 |
|       demodulator           |     0.004 |
|       inputfilter           |     0.003 |
|       iq_fgen               |     0.018 |
|       iqfilter[0]           |     0.008 |
|       iqfilter[1]           |     0.008 |
|       modulator             |     0.010 |
|     genblk6[7].iq_2_outputs |     0.077 |
|       demodulator           |     0.004 |
|       inputfilter           |     0.003 |
|       iq_fgen               |     0.018 |
|       iqfilter[0]           |     0.016 |
|       iqfilter[1]           |     0.016 |
|       modulator             |     0.012 |
|   i_hk                      |     0.001 |
|   i_ps                      |     1.318 |
|     axi_slave_gp0           |     0.002 |
|     system_i                |     1.314 |
|       system_i              |     1.314 |
|   i_scope                   |     0.051 |
|   pll                       |     0.097 |
|   pwm[0]                    |     0.002 |
|   pwm[1]                    |     0.002 |
|   pwm[2]                    |     0.002 |
|   pwm[3]                    |     0.002 |
+-----------------------------+-----------+